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The Effect of Annealing on Argon Implanted Edge Terminations for 4H-SiC Schottky Diodes

MRS proceedings, 1999, Vol.572, Article 129

1999

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Measurement of the residual macro and microstrain in strained Si/SiGe using Raman spectroscopy

MRS proceedings, 2004, Vol.809, Article B3.4

2004

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Optimisation of channel thickness in strained Si/SiGe MOSFETs

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003, 2003, p.501-504

2003

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A novel sensor for the direct measurement of process induced residual stress in interconnects

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003, 2003, p.115-118

2003

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Oxidation Modelling for SiC

MRS proceedings, 1999, Vol.572, Article 135

1999

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High Speed Deep Sub-Micron MOSFET using High Mobility Strained Silicon Channel

ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference, 1995, p.109-112

1995

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Noise performance in strained Si heterojunction bipolar transistors

2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2011, p.271-274

2011

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Simple Computer Modeling of the Grain Microstructure of Al-4wt%Cu Interconnection Lines

MRS proceedings, 1997, Vol.472, Article 191

1997

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Analysis of Electromigration Lifetime Measurements using Microscopic Polycrystalline Computer Simulation

ESSDERC '94: 24th European Solid State Device Research Conference, 1994, p.613-616

1994

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Demonstration of a Sub-micron Damascene Cu/Low-k Mechanical Sensor to Monitor Stress in BEOL Metallization

2009 IEEE International Conference on Microelectronic Test Structures, 2009, p.31-35

2009

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Improved analog performance of strained Si n-MOSFETs on thin SiGe strained relaxed buffers

ESSDERC 2008 - 38th European Solid-State Device Research Conference, 2008, p.99-102

2008

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Influence of barriers on the reliability of dual damascene copper contacts

2008 IEEE International Reliability Physics Symposium, 2008, p.677-678

2008

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Temperature non-uniformities in a silicon test square during rapid thermal processing

ESSDERC '90: 20th European Solid State Device Research Conference, 1990, p.69-72

1990

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Analysis of Gate Leakage in Strained Si MOSFETs

ECS transactions, 2006, Vol.3 (7), p.1001-1012

2006

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Test chip for the development and evaluation of test structures for measuring stress in metal interconnect

Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516), 2004, p.69-73

2004

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Performance limits of deep submicron buried channel delta doped MOSFETs

27th European Solid-State Device Research Conference, 1997, p.644-647

1997

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Piezomobility description of strain-induced mobility

2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008, p.464-467

2008

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Modeling the Mechanisms of Cu-Enhanced Median Time to Failure in Al-Cu Interconnects Under Electromigration

MRS proceedings, 1997, Vol.473, Article 317

1997

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Direct Correlation Between Grain Configuration and Electromigration Damage Development

MRS proceedings, 1996, Vol.428, Article 249

1996

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GaAs Schottky Gate bipolar transistors for high voltage power switching applications

27th European Solid-State Device Research Conference, 1997, p.548-551

1997

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Analysis of Geometrical and Microstructural Effects on Void Formation in Metallization: Observation and Modelling

MRS proceedings, 1996, Vol.428, Article 243

1996

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Semiconductor technology computer aided design

3rd International Conference on Computation in Electromagnetics (CEM 96), 1996, p.235-240

O'Neill, A.G

1996

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Synchrotron measurement of the effect of dielectric porosity and air gaps on the stress in advanced Cu/Low-k interconnects

2009 IEEE International Interconnect Technology Conference, 2009, p.72-74

2009

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New 3D Polycrystalline Model of Electromigration Induced Voiding at Interconnect Vias

ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference, 1996, p.913-916

1996

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Calibration and optimization of interconnect based MEMS test structures for predicting thermo-mechanical stress in metallization

2004 IEEE International Reliability Physics Symposium. Proceedings, 2004, p.255-258

2004

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The Effect of Annealing on Argon Implanted Edge Terminations for 4H-SiC Schottky Diodes

Measurement of the residual macro and microstrain in strained Si/SiGe using Raman spectroscopy

Optimisation of channel thickness in strained Si/SiGe MOSFETs

A novel sensor for the direct measurement of process induced residual stress in interconnects

Oxidation Modelling for SiC

High Speed Deep Sub-Micron MOSFET using High Mobility Strained Silicon Channel

Noise performance in strained Si heterojunction bipolar transistors

Simple Computer Modeling of the Grain Microstructure of Al-4wt%Cu Interconnection Lines

Analysis of Electromigration Lifetime Measurements using Microscopic Polycrystalline Computer Simulation

Demonstration of a Sub-micron Damascene Cu/Low-k Mechanical Sensor to Monitor Stress in BEOL Metallization

Improved analog performance of strained Si n-MOSFETs on thin SiGe strained relaxed buffers

Influence of barriers on the reliability of dual damascene copper contacts

Temperature non-uniformities in a silicon test square during rapid thermal processing

Analysis of Gate Leakage in Strained Si MOSFETs

Test chip for the development and evaluation of test structures for measuring stress in metal interconnect

Performance limits of deep submicron buried channel delta doped MOSFETs

Piezomobility description of strain-induced mobility

Modeling the Mechanisms of Cu-Enhanced Median Time to Failure in Al-Cu Interconnects Under Electromigration

Direct Correlation Between Grain Configuration and Electromigration Damage Development

GaAs Schottky Gate bipolar transistors for high voltage power switching applications

Analysis of Geometrical and Microstructural Effects on Void Formation in Metallization: Observation and Modelling

Semiconductor technology computer aided design

Synchrotron measurement of the effect of dielectric porosity and air gaps on the stress in advanced Cu/Low-k interconnects

New 3D Polycrystalline Model of Electromigration Induced Voiding at Interconnect Vias

Calibration and optimization of interconnect based MEMS test structures for predicting thermo-mechanical stress in metallization

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