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Bidirectional converter uniyfiying ac-to-dc power factor corrected converter and buck-boost dc-to-dc converter for a V2H application

2013 IEEE 10th International Conference on Power Electronics and Drive Systems (PEDS), 2013, p.814-817

2013

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A 72-channel Resistive-sensor Interface IC with High Energy Efficiency and a Wide Input Range

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.204-206

2018

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An Indirect Time-of-Flight Sensor with Adaptive Multiple Sampling for High Depth Precision

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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Bifunctional Characteristics of Al2O3 supported Ni in the HI Decomposition of Sulfur-Iodine Process

MATEC Web of Conferences, 2016, Vol.67, p.06063

2016

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13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.234-236

2024

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A 640×480 Indirect Time-of-Flight Image Sensor with Tetra Pixel Architecture for Tap Mismatch Calibration and Motion Artifact Suppression

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.44-45

2022

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22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.330-332

2020

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Real Time 3D Pose Estimation of Both Human Hands via RGB-Depth Camera and Deep Convolutional Neural Networks

7th International Conference on the Development of Biomedical Engineering in Vietnam (BME7), p.467-471

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25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.346-348

2021

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Dependence of device performances on fin dimensions in AlGaN/GaN recessed-gate nanoscale FinFET

The 18th IEEE International Symposium on Consumer Electronics (ISCE 2014), 2014, p.1-2

2014

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A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.278-613

2008

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Ontology-Based Edutainment System

Computational Science and Its Applications - ICCSA 2006, 2006, p.288-297

2006

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TELAT: An Educational Authoring Tool

Intelligent Tutoring Systems, 2006, p.750-752

2006

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23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.394-395

2017

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Towards Brain-based Interface for Communication and Control by Skin Touch

2023 11th International Winter Conference on Brain-Computer Interface (BCI), 2023, p.1-5

2023

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A \mathbf\times \mathbf Indirect Time-of-Flight Sensor with Pixel-Level Adaptive \Delta\Sigma-Operations for Background Light Cancellation

2023 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2023, p.1-3

2023

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A 3.1-μW BJT-Based CMOS Temperature-to-Frequency Converter with Untrimmed Inaccuracy of ±1°C (3σ) from -40°C to 140°C

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2021, p.1-3

2021

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23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.390-391

2017

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Effects of Low-Cost Salt Bath Nitrification Method on the Stainless Steel as Bipolar Plates for PEMFC

ECS transactions, 2011, Vol.35 (32), p.85-89

2011

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18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution

2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, p.314-315

2016

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Photodissociation Dynamics of Acetone in the Gas Phase and in Solution Studied by Transient Absorption and Femtosecond Stimulated Raman Spectroscopy

XXII International Conference, 2010, Vol.1267, p.294-294

2010

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LayNet: Layout Size Prediction for Memory Design Using Graph Neural Networks in Early Design Stage

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 2024, p.484-490

2024

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18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, p.316-317

2016

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Design and Performance Evaluation of Binary Code Packing for Protecting Embedded Software against Reverse Engineering

2010 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2010, p.80-86

2010

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Bidirectional converter uniyfiying ac-to-dc power factor corrected converter and buck-boost dc-to-dc converter for a V2H application

A 72-channel Resistive-sensor Interface IC with High Energy Efficiency and a Wide Input Range

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

An Indirect Time-of-Flight Sensor with Adaptive Multiple Sampling for High Depth Precision

Bifunctional Characteristics of Al2O3 supported Ni in the HI Decomposition of Sulfur-Iodine Process

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process

A 640×480 Indirect Time-of-Flight Image Sensor with Tetra Pixel Architecture for Tap Mismatch Calibration and Motion Artifact Suppression

22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme

Real Time 3D Pose Estimation of Both Human Hands via RGB-Depth Camera and Deep Convolutional Neural Networks

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM

Dependence of device performances on fin dimensions in AlGaN/GaN recessed-gate nanoscale FinFET

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

Ontology-Based Edutainment System

TELAT: An Educational Authoring Tool

23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices

Towards Brain-based Interface for Communication and Control by Skin Touch

A \mathbf\times \mathbf Indirect Time-of-Flight Sensor with Pixel-Level Adaptive \Delta\Sigma-Operations for Background Light Cancellation

A 3.1-μW BJT-Based CMOS Temperature-to-Frequency Converter with Untrimmed Inaccuracy of ±1°C (3σ) from -40°C to 140°C

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

Effects of Low-Cost Salt Bath Nitrification Method on the Stainless Steel as Bipolar Plates for PEMFC

18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution

Photodissociation Dynamics of Acetone in the Gas Phase and in Solution Studied by Transient Absorption and Femtosecond Stimulated Raman Spectroscopy

LayNet: Layout Size Prediction for Memory Design Using Graph Neural Networks in Early Design Stage

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

Design and Performance Evaluation of Binary Code Packing for Protecting Embedded Software against Reverse Engineering

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