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Improving hash join performance through prefetching

ACM transactions on database systems, 2007-08, Vol.32 (3), p.17

2007

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CacheInspector: Reverse Engineering Cache Resources in Public Clouds

ACM transactions on architecture and code optimization, 2021-09, Vol.18 (3), p.1-25

2021

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Revisiting PM-Based B ^+-Tree With Persistent CPU Cache

IEEE transactions on parallel and distributed systems, 2024-05, Vol.35 (5), p.796-813

2024

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Preventing cache-based side-channel attacks in a cloud environment

IEEE transactions on cloud computing, 2014-10, Vol.2 (4), p.395-408

2014

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DBI, debuggers, VM: gotta catch them all: How to escape or fool debuggers with internal architecture CPU flaws?

Journal of computer virology and hacking techniques, 2021-06, Vol.17 (2), p.105-117

2021

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HAP: Hybrid-Memory-Aware Partition in Shared Last-Level Cache

ACM transactions on architecture and code optimization, 2017-09, Vol.14 (3), p.1-25

2017

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MBZip: Multiblock Data Compression

ACM transactions on architecture and code optimization, 2017-12, Vol.14 (4), p.1-29

2017

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Self-Spectre, Write-Execute and the Hidden State

Tatra Mountains mathematical publications, 2019-08, Vol.73 (1), p.131-144

Morse, Gregory

2019

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XY-Type GPU Cache: Exploiting Spatial Localities in both X and Y Directions to Avoid Conflict Miss

Chinese Journal of Electronics, 2015-01, Vol.24 (1), p.88-95

Zhang, Jun

2015

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A Novel Approach to Prevent Cache-based Side-Channel Attack in the Cloud

Procedia technology, 2016, Vol.25, p.232-239

2016

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Highly efficient parallel direct solver for solving dense complex matrix equations from method of moments

Journal of engineering (Stevenage, England), 2017-04, Vol.2017 (4), p.69-71

2017

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Finite Automata Implementations Considering CPU Cache

Acta polytechnica (Prague, Czech Republic : 1992), 2007-01, Vol.47 (6)

Holub, J.

2007

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CPU cache prefetching: Timing evaluation of hardware implementations

IEEE transactions on computers, 1998-05, Vol.47 (5), p.509-526

1998

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Java runtime systems: characterization and architectural implications

IEEE transactions on computers, 2001-02, Vol.50 (2), p.131-146

2001

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On the total energy consumption of scalable cache-aided multi-CPU cell-free massive MIMO systems

Digital signal processing, 2024-11, Vol.154, p.104669, Article 104669

2024

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CPU Scheduling for Power/Energy Management on Multicore Processors Using Cache Miss and Context Switch Data

IEEE transactions on parallel and distributed systems, 2014-05, Vol.25 (5), p.1190-1199

2014

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Exploring Time-Predictable and High-Performance Last-Level Caches for Hard Real-Time Integrated CPU-GPU Processors

Journal of computing science and engineering : JCSE, 2020-09, Vol.14 (3), p.89-101

2020

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MRAM-Based Cache System Design and Policy Optimization for RISC-V Multi-Core CPUs

IEEE transactions on magnetics, 2023-06, Vol.59 (6), p.1-14

2023

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Improving CPU and GPU Performance through Sample-Based Dynamic LLC Bypassing

Journal of computing science and engineering : JCSE, 2018-06, Vol.12 (2), p.50-62

2018

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Meltdown-type attacks are still feasible in the wall of kernel page-Table isolation

Computers & security, 2022-02, Vol.113, p.102556, Article 102556

2022

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A Survey of Cache Bypassing Techniques

Journal of low power electronics and applications, 2016-04, Vol.6 (2), p.5

Mittal, Sparsh

2016

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The semantics of shared memory in Intel CPU/FPGA systems

Proceedings of ACM on programming languages, 2021-10, Vol.5 (OOPSLA), p.1-28

2021

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SIMULADOR DE UCP COM SUPORTE À MEMÓRIA CACHE E PIPELINE

Colloquium Exactarum (Online), 2014-10, Vol.6 (3), p.10-25

2014

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Filter cache: filtering useless cache blocks for a small but efficient shared last-level cache

The Journal of supercomputing, 2020-10, Vol.76 (10), p.7521-7544

2020

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Survey on memory management techniques in heterogeneous computing systems

Chronic diseases and translational medicine, 2020-03, Vol.14 (2), p.47-60

2020

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Improving hash join performance through prefetching

CacheInspector: Reverse Engineering Cache Resources in Public Clouds

Revisiting PM-Based B ^+-Tree With Persistent CPU Cache

Preventing cache-based side-channel attacks in a cloud environment

DBI, debuggers, VM: gotta catch them all: How to escape or fool debuggers with internal architecture CPU flaws?

HAP: Hybrid-Memory-Aware Partition in Shared Last-Level Cache

MBZip: Multiblock Data Compression

Self-Spectre, Write-Execute and the Hidden State

XY-Type GPU Cache: Exploiting Spatial Localities in both X and Y Directions to Avoid Conflict Miss

A Novel Approach to Prevent Cache-based Side-Channel Attack in the Cloud

Highly efficient parallel direct solver for solving dense complex matrix equations from method of moments

Finite Automata Implementations Considering CPU Cache

CPU cache prefetching: Timing evaluation of hardware implementations

Java runtime systems: characterization and architectural implications

On the total energy consumption of scalable cache-aided multi-CPU cell-free massive MIMO systems

CPU Scheduling for Power/Energy Management on Multicore Processors Using Cache Miss and Context Switch Data

Exploring Time-Predictable and High-Performance Last-Level Caches for Hard Real-Time Integrated CPU-GPU Processors

MRAM-Based Cache System Design and Policy Optimization for RISC-V Multi-Core CPUs

Improving CPU and GPU Performance through Sample-Based Dynamic LLC Bypassing

Meltdown-type attacks are still feasible in the wall of kernel page-Table isolation

A Survey of Cache Bypassing Techniques

The semantics of shared memory in Intel CPU/FPGA systems

SIMULADOR DE UCP COM SUPORTE À MEMÓRIA CACHE E PIPELINE

Filter cache: filtering useless cache blocks for a small but efficient shared last-level cache

Survey on memory management techniques in heterogeneous computing systems

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