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Chip Design and Verification in a Computer Engineering Education

Computer (Long Beach, Calif.), 2023-11, Vol.56 (11), p.20-29

2023

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A Java processor architecture for embedded real-time systems

Journal of systems architecture, 2008, Vol.54 (1), p.265-286

Schoeberl, Martin

2008

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Predictable and optimized single-path code for predicated processors

Journal of systems architecture, 2024-09, Vol.154, p.103214, Article 103214

2024

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Patmos: a time-predictable microprocessor

Real-time systems, 2018-04, Vol.54 (2), p.389-423

2018

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Time-Predictable Computer Architecture

EURASIP journal on embedded systems, 2009, Vol.2009 (1), p.1-17

Schoeberl, Martin

2009

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A Hardware Abstraction Layer in Java

ACM transactions on embedded computing systems, 2011-11, Vol.10 (4), p.1-40

2011

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Compiling for time-predictability with dual-issue single-path code

Journal of systems architecture, 2021-09, Vol.118, p.102230, Article 102230

2021

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Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

IEEE transactions on very large scale integration (VLSI) systems, 2016-02, Vol.24 (2), p.479-492

2016

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A real-time Java chip-multiprocessor

ACM transactions on embedded computing systems, 2010-08, Vol.10 (1), p.1-34

2010

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Comparing timed-division multiplexing and best-effort networks-on-chip

Journal of systems architecture, 2022-12, Vol.133, p.102766, Article 102766

2022

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T-CREST: Time-predictable multi-core architecture for embedded systems

Journal of systems architecture, 2015-10, Vol.61 (9), p.449-471

2015

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A time-predictable open-source TTEthernet end-system

Journal of systems architecture, 2020-09, Vol.108, p.101744, Article 101744

2020

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Direct garbage collection: two-fold speedup for managed language embedded systems

International journal of embedded systems, 2018, Vol.10 (5), p.394

2018

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Hardware support for CSP on a Java chip multiprocessor

Microprocessors and microsystems, 2013-06, Vol.37 (4-5), p.472-481

2013

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Verification of Chisel Hardware Designs with ChiselVerify

Microprocessors and microsystems, 2023-02, Vol.96, p.104737, Article 104737

2023

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Scheduling of hard real-time garbage collection

Real-time systems, 2010-08, Vol.45 (3), p.176-213

Schoeberl, Martin

2010

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Using dynamic partial reconfiguration of FPGAs in real-Time systems

Microprocessors and microsystems, 2018-09, Vol.61, p.198-206

2018

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Hardlock: Real-time multicore locking

Journal of systems architecture, 2019-08, Vol.97, p.467-476

2019

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Data cache organization for accurate timing analysis

Real-time systems, 2013, Vol.49 (1), p.1-28

2013

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Worst-case execution time analysis for a Java processor

Software, practice & experience, 2010-05, Vol.40 (6), p.507-542

2010

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Safety-critical Java with cyclic executives on chip-multiprocessors

Concurrency and computation, 2012-06, Vol.24 (8), p.772-788

2012

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Time-predictable synchronization support with a shared scratchpad memory

Microprocessors and microsystems, 2019-02, Vol.64, p.34-42

2019

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Nonblocking real-time garbage collection

ACM transactions on embedded computing systems, 2010-08, Vol.10 (1), p.1-28

2010

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Worst-case execution time analysis-driven object cache design

Concurrency and computation, 2012-06, Vol.24 (8), p.753-771

2012

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Time-predictable distributed shared on-chip memory

Microprocessors and microsystems, 2019-11, Vol.71, p.102896, Article 102896

2019

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Chip Design and Verification in a Computer Engineering Education

A Java processor architecture for embedded real-time systems

Predictable and optimized single-path code for predicated processors

Patmos: a time-predictable microprocessor

Time-Predictable Computer Architecture

A Hardware Abstraction Layer in Java

Compiling for time-predictability with dual-issue single-path code

Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

A real-time Java chip-multiprocessor

Comparing timed-division multiplexing and best-effort networks-on-chip

T-CREST: Time-predictable multi-core architecture for embedded systems

A time-predictable open-source TTEthernet end-system

Direct garbage collection: two-fold speedup for managed language embedded systems

Hardware support for CSP on a Java chip multiprocessor

Verification of Chisel Hardware Designs with ChiselVerify

Scheduling of hard real-time garbage collection

Using dynamic partial reconfiguration of FPGAs in real-Time systems

Hardlock: Real-time multicore locking

Data cache organization for accurate timing analysis

Worst-case execution time analysis for a Java processor

Safety-critical Java with cyclic executives on chip-multiprocessors

Time-predictable synchronization support with a shared scratchpad memory

Nonblocking real-time garbage collection

Worst-case execution time analysis-driven object cache design

Time-predictable distributed shared on-chip memory

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