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Scalable Effort Hardware Design

IEEE transactions on very large scale integration (VLSI) systems, 2014-09, Vol.22 (9), p.2004-2016

2014

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An Energy-Efficient Heterogeneous System for Embedded Learning and Classification

IEEE embedded systems letters, 2011-03, Vol.3 (1), p.42-45

2011

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Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC

IEEE transactions on very large scale integration (VLSI) systems, 2007-06, Vol.15 (6), p.699-710

2007

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A Massively Parallel, Energy Efficient Programmable Accelerator for Learning and Classification

ACM transactions on architecture and code optimization, 2012-03, Vol.9 (1), p.1-30

2012

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A transitive closure algorithm for test generation

IEEE transactions on computer-aided design of integrated circuits and systems, 1993-07, Vol.12 (7), p.1015-1028

1993

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Primitive delay faults: identification, testing, and design for testability

IEEE transactions on computer-aided design of integrated circuits and systems, 1999-06, Vol.18 (6), p.669-684

1999

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Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling

ACM transactions on embedded computing systems, 2013-05, Vol.12 (2s), p.1-23

2013

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Testable Path Delay Fault Cover for Sequential Circuits

Journal of Information Science and Engineering, 2000-09, Vol.16 (5), p.673-686

2000

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Energy models for delay testing

IEEE transactions on computer-aided design of integrated circuits and systems, 1995-06, Vol.14 (6), p.728-739

1995

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A Practical Vector Restoration Technique for Large Sequential Circuits

Journal of electronic testing, 2000-10, Vol.16 (5), p.521

2000

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Design of testable sequential circuits by repositioning flip-flops

Journal of electronic testing, 1995-08, Vol.7 (1-2), p.105-114

1995

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An exact algorithm for selecting partial scan flip-flops

Journal of electronic testing, 1995-08, Vol.7 (1-2), p.83-93

1995

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Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-10, Vol.25 (10), p.2193-2206

2006

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Synthesis of initializable asynchronous circuits

IEEE transactions on very large scale integration (VLSI) systems, 1996-06, Vol.4 (2), p.254-263

1996

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Finite state machine synthesis with fault tolerant test function

Journal of electronic testing, 1993-02, Vol.4 (1), p.57-69

1993

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A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-08, Vol.25 (8), p.1555-1564

2006

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Energy minimization and design for testability

Journal of electronic testing, 1994-02, Vol.5 (1), p.57-66

1994

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Tarazu: optimizing MapReduce on heterogeneous clusters

SIGPLAN notices, 2012-06, Vol.47 (4), p.61-74

2012

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Bottleneck removal algorithm for dynamic compaction in sequential circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 1997-10, Vol.16 (10), p.1157-1172

1997

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Resynthesis and retiming for optimum partial scan

IEEE transactions on computer-aided design of integrated circuits and systems, 1999-05, Vol.18 (5), p.621-630

1999

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Tarazu: optimizing MapReduce on heterogeneous clusters

Computer architecture news, 2012-04, Vol.40 (1), p.61-74

2012

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Test function embedding algorithms with application to interconnected finite state machines

IEEE transactions on computer-aided design of integrated circuits and systems, 1995-09, Vol.14 (9), p.1115-1127

1995

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Redundancy removal and test generation for circuits with non-Boolean primitives

IEEE transactions on computer-aided design of integrated circuits and systems, 1997-11, Vol.16 (11), p.1370-1377

1997

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Performance analysis of synchronized iterative algorithms on multiprocessor systems

IEEE transactions on parallel and distributed systems, 1992-11, Vol.3 (6), p.739-746

1992

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Toward massively parallel automatic test generation

IEEE transactions on computer-aided design of integrated circuits and systems, 1990-09, Vol.9 (9), p.981-994

1990

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Scalable Effort Hardware Design

An Energy-Efficient Heterogeneous System for Embedded Learning and Classification

Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC

A Massively Parallel, Energy Efficient Programmable Accelerator for Learning and Classification

A transitive closure algorithm for test generation

Primitive delay faults: identification, testing, and design for testability

Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling

Testable Path Delay Fault Cover for Sequential Circuits

Energy models for delay testing

A Practical Vector Restoration Technique for Large Sequential Circuits

Design of testable sequential circuits by repositioning flip-flops

An exact algorithm for selecting partial scan flip-flops

Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques

Synthesis of initializable asynchronous circuits

Finite state machine synthesis with fault tolerant test function

A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs

Energy minimization and design for testability

Tarazu: optimizing MapReduce on heterogeneous clusters

Bottleneck removal algorithm for dynamic compaction in sequential circuits

Resynthesis and retiming for optimum partial scan

Tarazu: optimizing MapReduce on heterogeneous clusters

Test function embedding algorithms with application to interconnected finite state machines

Redundancy removal and test generation for circuits with non-Boolean primitives

Performance analysis of synchronized iterative algorithms on multiprocessor systems

Toward massively parallel automatic test generation

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