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Staining Outcomes of Silver Diamine Fluoride as an Adjunct in Caries Risk Assessment: A Case Series Evaluation

The Journal of clinical pediatric dentistry, 2022-01, Vol.46 (1), p.6-11

2022

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Self-assembled monolayer-immobilized gold nanoparticles for WO3/TiO2 nanocomposite films to yield remarkably enhanced ultraviolet and visible-light photocatalytic activity

Materials letters, 2022-03, Vol.311, p.131604, Article 131604

2022

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Enhancement of Electromigration Reliability of Electroless-Plated Nanoscaled Copper Interconnects by Complete Encapsulation of a 1 nm-Thin Self-Assembled Monolayer

Journal of the Electrochemical Society, 2022-08, Vol.169 (8), p.82519

2022

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Communication—Defect-Free Filling of High Aspect Ratio Through Vias in Ultrathin Glass

Journal of the Electrochemical Society, 2019, Vol.166 (1), p.D3155-D3157

2019

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Activation of amino-based monolayers for electroless metallization of high-aspect-ratio through-silicon vias by using a simple ultrasonic-assisted plating solution

Applied surface science, 2018-05, Vol.440, p.209-216

2018

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Influence of Aminosilane Self-assembled Layers on the Adhesion of Electroless Nickel–Phosphorus on a Silicon Wafer

Sensors and materials, 2021-06, Vol.33 (6), p.1849

2021

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All-Solution-Processed Metallization of High Aspect Ratio Through Glass Vias (HAR-TGVs) with a High Adhesion Promoting Layer (APL)

2023 18th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2023, p.251-254

2023

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Low-cost 3DIC process technologies for wide-I/O memory cube

2015 International Symposium on VLSI Technology, Systems and Applications, 2015, p.1-2

2015

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Process integration of 3D Si interposer with double-sided active chip attachments

2013 IEEE 63rd Electronic Components and Technology Conference, 2013, p.86-93

2013

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Fine-pitch backside via-last TSV process with optimization on temporary glue and bonding conditions

2013 IEEE 63rd Electronic Components and Technology Conference, 2013, p.1811-1814

2013

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A novel fabrication process and measurement results of a 28GHz glass antenna with single TGV for 5G communication applications

2019 14th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2019, p.112-115

2019

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Challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer

2013 IEEE International 3D Systems Integration Conference (3DIC), 2013, p.1-5

2013

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Technologies and challenges of fine-pitch backside via-last 3DIC TSV process integration and its electrical characteristics and system applications

Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2014, p.1-2

2014

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Study of TSV filling performance with wide-range pattern densities by using a novel plating chamber with surface paddle agitation

2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2013, p.1-2

2013

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Backside-TSV process development and integration for 2∼3um small size TSV

2016 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2016, p.273-276

2016

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Implementation of memory stacking on logic controller by using 3DIC 300mm backside TSV process integration

2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2016, p.1-2

2016

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An innovative bumpless stacking with through silicon via for 3D Wafer-on-Wafer (WOW) integration

2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 2014, p.1853-1856

2014

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Very High Aspect Ratio (AR>10) through Glass Hole (TGH) Filling in Stagnant Condition By Using DC Plating for Advanced Interposer Applications

Meeting abstracts (Electrochemical Society), 2018-07, Vol.MA2018-02 (33), p.1139-1139

2018

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A Novel Synthesis Method of Cu Nanopartices and Their Applications Acting as Seed Layer of TSV

Meeting abstracts (Electrochemical Society), 2010-07, Vol.MA2010-02 (2), p.113-113

2010

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A Novel Synthesis Method of Cu Nanoparticles with High Stability and Their Applications Acting as Seed Layer of TSV

Meeting abstracts (Electrochemical Society), 2012-06, Vol.MA2012-02 (34), p.2746-2746

2012

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Electroless Deposition of Barrier and Seed Layers for TSV Metallization

Meeting abstracts (Electrochemical Society), 2011-03, Vol.MA2011-01 (27), p.1585-1585

2011

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Wet Processes for Filling through Silicon Vias and Butterfly Technology for Filling through Silicon Holes

Meeting abstracts (Electrochemical Society), 2011-03, Vol.MA2011-01 (27), p.1575-1575

2011

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Through Silicon Vias and Holes Metallization using CoWP and Cu Nanoparticles as Barrier and Seed Layers

International Symposium on Microelectronics, 2011-01, Vol.2011 (1), p.645-649

2011

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Through Silicon Vias and Holes Metallization by Cu Nanoparticles Coating and Cu Electrodeposition

Meeting abstracts (Electrochemical Society), 2010-07, Vol.MA2010-02 (32), p.2005-2005

2010

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Synthesis of perhydroisoquinoline derivatives mediated by ( η6-arene)Cr(CO) 3 complexes

Tetrahedron letters, 1997-10, Vol.38 (42), p.7387-7390

1997

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Staining Outcomes of Silver Diamine Fluoride as an Adjunct in Caries Risk Assessment: A Case Series Evaluation

Self-assembled monolayer-immobilized gold nanoparticles for WO3/TiO2 nanocomposite films to yield remarkably enhanced ultraviolet and visible-light photocatalytic activity

Enhancement of Electromigration Reliability of Electroless-Plated Nanoscaled Copper Interconnects by Complete Encapsulation of a 1 nm-Thin Self-Assembled Monolayer

Communication—Defect-Free Filling of High Aspect Ratio Through Vias in Ultrathin Glass

Activation of amino-based monolayers for electroless metallization of high-aspect-ratio through-silicon vias by using a simple ultrasonic-assisted plating solution

Influence of Aminosilane Self-assembled Layers on the Adhesion of Electroless Nickel–Phosphorus on a Silicon Wafer

All-Solution-Processed Metallization of High Aspect Ratio Through Glass Vias (HAR-TGVs) with a High Adhesion Promoting Layer (APL)

Low-cost 3DIC process technologies for wide-I/O memory cube

Process integration of 3D Si interposer with double-sided active chip attachments

Fine-pitch backside via-last TSV process with optimization on temporary glue and bonding conditions

A novel fabrication process and measurement results of a 28GHz glass antenna with single TGV for 5G communication applications

Challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer

Technologies and challenges of fine-pitch backside via-last 3DIC TSV process integration and its electrical characteristics and system applications

Study of TSV filling performance with wide-range pattern densities by using a novel plating chamber with surface paddle agitation

Backside-TSV process development and integration for 2∼3um small size TSV

Implementation of memory stacking on logic controller by using 3DIC 300mm backside TSV process integration

An innovative bumpless stacking with through silicon via for 3D Wafer-on-Wafer (WOW) integration

Very High Aspect Ratio (AR>10) through Glass Hole (TGH) Filling in Stagnant Condition By Using DC Plating for Advanced Interposer Applications

A Novel Synthesis Method of Cu Nanopartices and Their Applications Acting as Seed Layer of TSV

A Novel Synthesis Method of Cu Nanoparticles with High Stability and Their Applications Acting as Seed Layer of TSV

Electroless Deposition of Barrier and Seed Layers for TSV Metallization

Wet Processes for Filling through Silicon Vias and Butterfly Technology for Filling through Silicon Holes

Through Silicon Vias and Holes Metallization using CoWP and Cu Nanoparticles as Barrier and Seed Layers

Through Silicon Vias and Holes Metallization by Cu Nanoparticles Coating and Cu Electrodeposition

Synthesis of perhydroisoquinoline derivatives mediated by ( η6-arene)Cr(CO) 3 complexes

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