UB Paderborn / Katalog / Suche / in CDI

Effects of inductance on the propagation delay and repeater insertion in VLSI circuits

IEEE transactions on very large scale integration (VLSI) systems, 2000-04, Vol.8 (2), p.195-206

2000

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On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions

IEEE journal of selected topics in quantum electronics, 2006-11, Vol.12 (6), p.1699-1705

2006

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Clock distribution networks in synchronous digital integrated circuits

Proceedings of the IEEE, 2001-05, Vol.89 (5), p.665-692

Friedman, E.G.

2001

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Figures of merit to characterize the importance of on-chip inductance

IEEE transactions on very large scale integration (VLSI) systems, 1999-12, Vol.7 (4), p.442-449

1999

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An RLC interconnect model based on fourier analysis

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-02, Vol.24 (2), p.170-183

2005

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TEAM: ThrEshold Adaptive Memristor Model

IEEE transactions on circuits and systems. I, Regular papers, 2013-01, Vol.60 (1), p.211-221

2013

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The International Study of Pregnancy Outcome in Women with Maternal Phenylketonuria: Report of a 12-year study

American journal of obstetrics and gynecology, 2000-02, Vol.182 (2), p.326-333

2000

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Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints

IEEE transactions on very large scale integration (VLSI) systems, 2006-02, Vol.14 (2), p.161-172

2006

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Domino logic with variable threshold voltage keeper

IEEE transactions on very large scale integration (VLSI) systems, 2003-12, Vol.11 (6), p.1080-1093

2003

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Sleep switch dual threshold Voltage domino logic with reduced standby leakage current

IEEE transactions on very large scale integration (VLSI) systems, 2004-05, Vol.12 (5), p.485-496

2004

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Dynamically tuning processor resources with adaptive processing

Computer (Long Beach, Calif.), 2003-12, Vol.36 (12), p.49-58

2003

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Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

IEEE transactions on electron devices, 2009-09, Vol.56 (9), p.1873-1881

2009

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Low-voltage-swing monolithic dc-dc conversion

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2004-05, Vol.51 (5), p.241-248

2004

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Scaling trends of on-chip power distribution noise

IEEE transactions on very large scale integration (VLSI) systems, 2004-04, Vol.12 (4), p.386-394

2004

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Heterogeneous Methodology for Energy Efficient Distribution of On-Chip Power Supplies

IEEE transactions on power electronics, 2013-09, Vol.28 (9), p.4267-4280

2013

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Equivalent Elmore delay for RLC trees

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-01, Vol.19 (1), p.83-97

2000

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3-D Topologies for Networks-on-Chip

IEEE transactions on very large scale integration (VLSI) systems, 2007-10, Vol.15 (10), p.1081-1090

2007

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Tools for the computer-aided design of multigigahertz superconducting digital circuits

IEEE transactions on applied superconductivity, 1999-03, Vol.9 (1), p.18-38

1999

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Decoupling capacitors for multi-voltage power distribution systems

IEEE transactions on very large scale integration (VLSI) systems, 2006-03, Vol.14 (3), p.217-228

2006

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Simultaneous switching noise in on-chip CMOS power distribution networks

IEEE transactions on very large scale integration (VLSI) systems, 2002-08, Vol.10 (4), p.487-493

2002

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Three-dimensional Integrated Circuit Design

1, 2010

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Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor

IEEE transactions on very large scale integration (VLSI) systems, 2003-06, Vol.11 (3), p.514-522

2003

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Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Proceedings of the IEEE, 2009-01, Vol.97 (1), p.123-140

2009

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Inductive properties of high-performance power distribution grids

IEEE transactions on very large scale integration (VLSI) systems, 2002-12, Vol.10 (6), p.762-776

2002

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Exponentially tapered H-tree clock distribution networks

IEEE transactions on very large scale integration (VLSI) systems, 2005-08, Vol.13 (8), p.971-975

2005

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Effects of inductance on the propagation delay and repeater insertion in VLSI circuits

On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions

Clock distribution networks in synchronous digital integrated circuits

Figures of merit to characterize the importance of on-chip inductance

An RLC interconnect model based on fourier analysis

TEAM: ThrEshold Adaptive Memristor Model

The International Study of Pregnancy Outcome in Women with Maternal Phenylketonuria: Report of a 12-year study

Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints

Domino logic with variable threshold voltage keeper

Sleep switch dual threshold Voltage domino logic with reduced standby leakage current

Dynamically tuning processor resources with adaptive processing

Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

Low-voltage-swing monolithic dc-dc conversion

Scaling trends of on-chip power distribution noise

Heterogeneous Methodology for Energy Efficient Distribution of On-Chip Power Supplies

Equivalent Elmore delay for RLC trees

3-D Topologies for Networks-on-Chip

Tools for the computer-aided design of multigigahertz superconducting digital circuits

Decoupling capacitors for multi-voltage power distribution systems

Simultaneous switching noise in on-chip CMOS power distribution networks

Three-dimensional Integrated Circuit Design

Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Inductive properties of high-performance power distribution grids

Exponentially tapered H-tree clock distribution networks

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