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High efficiency and high linearity InGaP/GaAs HBT power amplifiers: matching techniques of source and load impedance to improve phase distortion and linearity

IEEE transactions on electron devices, 1998-06, Vol.45 (6), p.1196-1200

1998

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Gate Capacitance Modeling and Diameter-Dependent Performance of Nanowire MOSFETs

IEEE transactions on electron devices, 2012-04, Vol.59 (4), p.1037-1045

2012

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Experimental Details of a Steep-Slope Ferroelectric InGaAs Tunnel-FET With High-Quality PZT and Modeling Insights in the Transient Polarization

IEEE transactions on electron devices, 2020-01, Vol.67 (1), p.377-382

2020

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EOT of 0.62 nm and High Electron Mobility in La-silicate/Si Structure Based nMOSFETs Achieved by Utilizing Metal-Inserted Poly-Si Stacks and Annealing at High Temperature

IEEE transactions on electron devices, 2012-02, Vol.59 (2), p.269-276

2012

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Electron-Hole Bilayer TFET: Experiments and Comments

IEEE transactions on electron devices, 2014-08, Vol.61 (8), p.2674-2681

2014

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The Effect of Fluorine Doping in the Charge Trapping Layer on Device Characteristics and Reliability of E-Mode GaN MIS-HEMTs

IEEE transactions on electron devices, 2024-06, Vol.71 (6), p.3603-3608

2024

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CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET

IEEE transactions on electron devices, 2014-09, Vol.61 (9), p.3066-3074

2014

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Layout Dependence Modeling for 45-nm CMOS With Stress-Enhanced Technique

IEEE transactions on electron devices, 2009-09, Vol.56 (9), p.1991-1998

2009

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Gate Technology Contributions to Collapse of Drain Current in AlGaN/GaN Schottky HEMT

IEEE transactions on electron devices, 2014-03, Vol.61 (3), p.785-792

2014

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1.5 nm direct-tunneling gate oxide Si MOSFET's

IEEE transactions on electron devices, 1996-08, Vol.43 (8), p.1233-1242

1996

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Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI

IEEE transactions on electron devices, 1995-05, Vol.42 (5), p.915-922

1995

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Ultrathin gate oxide CMOS on [111] surface-oriented Si substrate

IEEE transactions on electron devices, 2002-09, Vol.49 (9), p.1597-1605

2002

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An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs

IEEE transactions on electron devices, 2000-12, Vol.47 (12), p.2410-2419

2000

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Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: uniformity, reliability, and dopant penetration of the gate oxide

IEEE transactions on electron devices, 1998-03, Vol.45 (3), p.691-700

1998

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A 40 nm gate length n-MOSFET

IEEE transactions on electron devices, 1995-10, Vol.42 (10), p.1822-1830

1995

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Cutoff frequency and propagation delay time of 1.5-nm gate oxide CMOS

IEEE transactions on electron devices, 2001-06, Vol.48 (6), p.1165-1174

2001

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A new charge pumping method for determining the spatial distribution of hot-carrier-induced fixed charge in p-MOSFETs

IEEE transactions on electron devices, 1993-10, Vol.40 (10), p.1768-1779

1993

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0.15-μm RF CMOS technology compatible with logic CMOS for low-voltage operation

IEEE transactions on electron devices, 1998-03, Vol.45 (3), p.737-742

1998

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Scaling the MOS transistor below 0.1 μm : methodology, device structures, and technology requirements

IEEE transactions on electron devices, 1994-06, Vol.41 (6), p.941-951

1994

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Ultrathin gate oxide CMOS with nondoped selective epitaxial Si channel layer

IEEE transactions on electron devices, 2001-06, Vol.48 (6), p.1136-1144

2001

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Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD with preheating

IEEE transactions on electron devices, 1998-03, Vol.45 (3), p.710-716

1998

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Power Si-MOSFET operating with high efficiency under low supply voltage

IEEE transactions on electron devices, 2000-12, Vol.47 (12), p.2385-2391

2000

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Analysis of hot-carrier-induced degradation mode on pMOSFET's

IEEE transactions on electron devices, 1990-06, Vol.37 (6), p.1487-1495

1990

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Analysis of the temperature dependence of hot-carrier-induced degradation in bipolar transistors for Bi-CMOS

IEEE transactions on electron devices, 1994-06, Vol.41 (6), p.978-987

1994

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Thermal stability of CoSi2 film for CMOS salicide

IEEE transactions on electron devices, 2000-11, Vol.47 (11), p.2208

2000

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High efficiency and high linearity InGaP/GaAs HBT power amplifiers: matching techniques of source and load impedance to improve phase distortion and linearity

Gate Capacitance Modeling and Diameter-Dependent Performance of Nanowire MOSFETs

Experimental Details of a Steep-Slope Ferroelectric InGaAs Tunnel-FET With High-Quality PZT and Modeling Insights in the Transient Polarization

EOT of 0.62 nm and High Electron Mobility in La-silicate/Si Structure Based nMOSFETs Achieved by Utilizing Metal-Inserted Poly-Si Stacks and Annealing at High Temperature

Electron-Hole Bilayer TFET: Experiments and Comments

The Effect of Fluorine Doping in the Charge Trapping Layer on Device Characteristics and Reliability of E-Mode GaN MIS-HEMTs

CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET

Layout Dependence Modeling for 45-nm CMOS With Stress-Enhanced Technique

Gate Technology Contributions to Collapse of Drain Current in AlGaN/GaN Schottky HEMT

1.5 nm direct-tunneling gate oxide Si MOSFET's

Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI

Ultrathin gate oxide CMOS on [111] surface-oriented Si substrate

An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs

Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: uniformity, reliability, and dopant penetration of the gate oxide

A 40 nm gate length n-MOSFET

Cutoff frequency and propagation delay time of 1.5-nm gate oxide CMOS

A new charge pumping method for determining the spatial distribution of hot-carrier-induced fixed charge in p-MOSFETs

0.15-μm RF CMOS technology compatible with logic CMOS for low-voltage operation

Scaling the MOS transistor below 0.1 μm : methodology, device structures, and technology requirements

Ultrathin gate oxide CMOS with nondoped selective epitaxial Si channel layer

Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD with preheating

Power Si-MOSFET operating with high efficiency under low supply voltage

Analysis of hot-carrier-induced degradation mode on pMOSFET's

Analysis of the temperature dependence of hot-carrier-induced degradation in bipolar transistors for Bi-CMOS

Thermal stability of CoSi2 film for CMOS salicide

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