UB Paderborn / Katalog / Suche / in CDI

1 – 22 von 22

Sortiert nach

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

IEEE journal of solid-state circuits, 2010-01, Vol.45 (1), p.111-119

2010

Volltextzugriff (PDF)

A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface

IEEE journal of solid-state circuits, 2017-06, Vol.52 (6), p.1563-1575

2017

Volltextzugriff (PDF)

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

IEEE journal of solid-state circuits, 2012-04, Vol.47 (4), p.981-989

2012

Volltextzugriff (PDF)

Simultaneous Reverse Body and Negative Word-Line Biasing Control Scheme for Leakage Reduction of DRAM

IEEE journal of solid-state circuits, 2011-10, Vol.46 (10), p.2396-2405

2011

Volltextzugriff (PDF)

Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH

IEEE journal of solid-state circuits, 2013-04, Vol.48 (4), p.948-959

2013

Volltextzugriff (PDF)

A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme

IEEE journal of solid-state circuits, 2009-08, Vol.44 (8), p.2222-2232

2009

Volltextzugriff (PDF)

Conditional-capture flip-flop for statistical power reduction

IEEE journal of solid-state circuits, 2001-08, Vol.36 (8), p.1263-1271

2001

Volltextzugriff (PDF)

A 0.13- \mu m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

IEEE journal of solid-state circuits, 2009-11, Vol.44 (11), p.3146-3162

2009

Volltextzugriff (PDF)

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.121-131, Article 121

2008

Volltextzugriff (PDF)

A 31 ns Random Cycle VCAT-Based 4F ^ DRAM With Manufacturability and Enhanced Cell Efficiency

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.880-888

2010

Volltextzugriff (PDF)

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

IEEE journal of solid-state circuits, 2011-01, Vol.46 (1), p.107-118

2011

Volltextzugriff (PDF)

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking

IEEE journal of solid-state circuits, 2012, Vol.47 (1), p.107-116

2012

Volltextzugriff (PDF)

A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces

IEEE journal of solid-state circuits, 2009-05, Vol.44 (5), p.1522-1530

2009

Volltextzugriff (PDF)

A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array

IEEE journal of solid-state circuits, 2008-11, Vol.43 (11), p.2381-2389

2008

Volltextzugriff (PDF)

A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control

IEEE journal of solid-state circuits, 2005-01, Vol.40 (1), p.223-232

2005

Volltextzugriff (PDF)

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 \times 128 I/Os Using TSV Based Stacking

IEEE journal of solid-state circuits, 2012-01, Vol.47 (1), p.107-116

2012

Volltextzugriff (PDF)

A 0.13-[Formula Omitted]m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

IEEE journal of solid-state circuits, 2009-11, Vol.44 (11), p.3146

2009

Volltextzugriff (PDF)

Correction on "A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme" [Aug 09 2222-2232]

IEEE journal of solid-state circuits, 2010-02, Vol.45 (2), p.497-497

2010

Volltextzugriff (PDF)

Correction on aA 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Schemea

IEEE journal of solid-state circuits, 2010-02, Vol.45 (2), p.497-497

2010

Volltextzugriff (PDF)

Correction on “A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme” [Aug 09 2222-2232

IEEE journal of solid-state circuits, 2010-02, Vol.45 (2), p.497-497

2010

Volltextzugriff (PDF)

A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme: SPECIAL ISSUE ON THE 2008 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE

IEEE journal of solid-state circuits, 2009, Vol.44 (8), p.2222-2232

2009

Volltextzugriff (PDF)

A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.880-888

2010

Volltextzugriff (PDF)

1 – 22 von 22

Suche als RSS-Feed

Aktive Filter

Zeitschrift / SerieIeee Journal Of Solid-State Circuits

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(22)
Mit Volltextzugriff
(22)

Publikationsform

Artikel
(22)

Sprache

Englisch
(22)

Erscheinungsjahr

n.n

Kollektion

IEEE Xplore
(22)
Ingenta
(22)

Menü

Weitere Dienste

Einstellungen

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

Simultaneous Reverse Body and Negative Word-Line Biasing Control Scheme for Leakage Reduction of DRAM

Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH

A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme

Conditional-capture flip-flop for statistical power reduction

A 0.13- \mu m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

A 31 ns Random Cycle VCAT-Based 4F ^ DRAM With Manufacturability and Enhanced Cell Efficiency

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking

A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces

A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array

A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 \times 128 I/Os Using TSV Based Stacking

A 0.13-[Formula Omitted]m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

Correction on "A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme" [Aug 09 2222-2232]

Correction on aA 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Schemea

Correction on “A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme” [Aug 09 2222-2232

A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme: SPECIAL ISSUE ON THE 2008 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE

A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency

Aktive Filter

Suchergebnisse filtern