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Differentially methylated gene regions between resistant and susceptible heat-phenotypes of the Pacific oyster Crassostrea gigas

Aquaculture, 2021-10, Vol.543, p.736923, Article 736923

2021

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Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation: 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings

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Agent-Based Thermal Management Using Real-Time I/O Communication Relocation for 3D Many-Cores

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, p.112-121

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Improving the Robustness of Self-timed SRAM to Variable Vdds

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, p.32-42

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Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, p.214-225

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NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, p.152-161

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A Framework for Architecture-Level Exploration of 3-D FPGA Platforms

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, p.298-307

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High Level Synthesis of Asynchronous Circuits from Data Flow Graphs

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, p.317-330

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Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, p.204-213

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Scallop growout using a new bottom-culture system

Aquaculture, 2000-09, Vol.189 (1), p.73-84

2000

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Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, p.267-277

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Architecture Extensions for Efficient Management of Scratch-Pad Memory

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, p.43-52

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Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, p.83-91

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Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels

21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011, 2011, p.278-287

2011

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Variability-Speed-Consumption Trade-off in Near Threshold Operation

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, p.308-316

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A System Level Approach to Multi-core Thermal Sensors Calibration

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, p.22-31

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Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, p.143-151

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Differentially methylated gene regions between resistant and susceptible heat-phenotypes of the Pacific oyster Crassostrea gigas

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation: 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings

Agent-Based Thermal Management Using Real-Time I/O Communication Relocation for 3D Many-Cores

Improving the Robustness of Self-timed SRAM to Variable Vdds

Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating

NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode

A Framework for Architecture-Level Exploration of 3-D FPGA Platforms

High Level Synthesis of Asynchronous Circuits from Data Flow Graphs

Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization

Scallop growout using a new bottom-culture system

Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits

Architecture Extensions for Efficient Management of Scratch-Pad Memory

Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology

Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels

Variability-Speed-Consumption Trade-off in Near Threshold Operation

A System Level Approach to Multi-core Thermal Sensors Calibration

Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique

A Secure D Flip-Flop against Side Channel Attacks

Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures

A Methodology for Power-Aware Transaction-Level Models of Systems-on-Chip Using UPF Standard Concepts

Using Silent Writes in Low-Power Traffic-Aware ECC

Energy Estimator for Weather Forecasts Dynamic Power Management of Wireless Sensor Networks

Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study

Performance-Driven Clustering of Asynchronous Circuits

Iterative Timing Analysis Considering Interdependency of Setup and Hold Times

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