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CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop

IEEE transactions on circuits and systems. I, Regular papers, 2023-12, Vol.70 (12), p.5316-5327

2023

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Energy- and Area-Efficient CMOS Synapse and Neuron for Spiking Neural Networks With STDP Learning

IEEE transactions on circuits and systems. I, Regular papers, 2022-09, Vol.69 (9), p.3632-3642

2022

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IEEE_Xplore

Low-Power High-Speed Sense-Amplifier-Based Flip-Flops With Conditional Bridging

IEEE access, 2023, Vol.11, p.121835-121844

2023

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A Fast Response PWM Buck Converter With Active Ramp Tracking Control in a Load Transient Period

IEEE transactions on circuits and systems. II, Express briefs, 2019-03, Vol.66 (3), p.467-471

2019

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IEEE_Xplore

How to Build a Memristive Integrate-and-Fire Model for Spiking Neuronal Signal Generation

IEEE transactions on circuits and systems. I, Regular papers, 2021-12, Vol.68 (12), p.4837-4850

2021

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IEEE_Xplore

Linearity Enhancement of VCO-Based Continuous-Time Delta-Sigma ADCs Using Digital Feedback Residue Quantization

Electronics (Basel), 2021-11, Vol.10 (22), p.2773

2021

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A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface

IEEE journal of solid-state circuits, 2017-06, Vol.52 (6), p.1563-1575

2017

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IEEE_Xplore

High-Efficiency DC–DC Converter with Charge-Recycling Gate-Voltage Swing Control

Energies (Basel), 2019-03, Vol.12 (5), p.899

2019

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Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application

IEEE transactions on very large scale integration (VLSI) systems, 2017-02, Vol.25 (2), p.779-782

2017

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IEEE_Xplore

Fast Output Voltage-Regulated PWM Buck Converter With an Adaptive Ramp Amplitude Control

IEEE transactions on circuits and systems. II, Express briefs, 2013-10, Vol.60 (10), p.712-716

2013

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IEEE_Xplore

Double-sampled ΔΣ modulator with 1.5-bit FIR feedback DAC for reduced noise folding and increased power efficiency

Electronics letters, 2016-04, Vol.52 (8), p.598-600

2016

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Simultaneous Reverse Body and Negative Word-Line Biasing Control Scheme for Leakage Reduction of DRAM

IEEE journal of solid-state circuits, 2011-10, Vol.46 (10), p.2396-2405

2011

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IEEE_Xplore

CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction

IEEE transactions on circuits and systems. II, Express briefs, 2009-01, Vol.56 (1), p.11-15

2009

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IEEE_Xplore

10T SRAM Using Half- V} Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage

IEEE transactions on very large scale integration (VLSI) systems, 2017-04, Vol.25 (4), p.1193-1203

2017

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IEEE_Xplore

Low-Voltage CMOS Differential Logic Style With Supply Voltage Approaching Device Threshold

IEEE transactions on circuits and systems. II, Express briefs, 2012-03, Vol.59 (3), p.173-177

2012

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IEEE_Xplore

Conditional-capture flip-flop for statistical power reduction

IEEE journal of solid-state circuits, 2001-08, Vol.36 (8), p.1263-1271

2001

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IEEE_Xplore

High-Speed Rail-to-Rail Class-AB Buffer Amplifier with Compact, Adaptive Biasing for FPD Applications

Electronics (Basel), 2020-12, Vol.9 (12), p.2018

2020

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Low-Voltage Bootstrapped CMOS Drivers With Efficient Conditional Bootstrapping

IEEE transactions on circuits and systems. II, Express briefs, 2008-06, Vol.55 (6), p.556-560

2008

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IEEE_Xplore

A line inversion-based stepwise data driving for low-power mobile TFT-LCDs

IEEE transactions on consumer electronics, 2010-05, Vol.56 (2), p.1002-1009

2010

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IEEE_Xplore

Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation

IEEE transactions on circuits and systems. II, Express briefs, 2009-08, Vol.56 (8), p.649-653

2009

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IEEE_Xplore

A 6 Gbps/pin Low‐Power Half‐Duplex Active Cross‐Coupled LVDS Transceiver with Switched Termination

ETRI Journal, 2008, 30(4), , pp.612-614

2008

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A DFE Receiver With Equalized VREF for Multidrop Single-Ended Signaling

IEEE transactions on circuits and systems. II, Express briefs, 2013-07, Vol.60 (7), p.412-416

2013

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IEEE_Xplore

CMOS Charge Pump With No Reversion Loss and Enhanced Drivability

IEEE transactions on very large scale integration (VLSI) systems, 2014-06, Vol.22 (6), p.1441-1445

2014

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IEEE_Xplore

Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2007-07, Vol.54 (7), p.601-605

2007

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IEEE_Xplore

10.4 A 5.8Gb/s adaptive integrating duobinary-based DFE receiver for multi-drop memory interface

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3

2015

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IEEE_Xplore

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CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop

Energy- and Area-Efficient CMOS Synapse and Neuron for Spiking Neural Networks With STDP Learning

Low-Power High-Speed Sense-Amplifier-Based Flip-Flops With Conditional Bridging

A Fast Response PWM Buck Converter With Active Ramp Tracking Control in a Load Transient Period

How to Build a Memristive Integrate-and-Fire Model for Spiking Neuronal Signal Generation

Linearity Enhancement of VCO-Based Continuous-Time Delta-Sigma ADCs Using Digital Feedback Residue Quantization

A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface

High-Efficiency DC–DC Converter with Charge-Recycling Gate-Voltage Swing Control

Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application

Fast Output Voltage-Regulated PWM Buck Converter With an Adaptive Ramp Amplitude Control

Double-sampled ΔΣ modulator with 1.5-bit FIR feedback DAC for reduced noise folding and increased power efficiency

Simultaneous Reverse Body and Negative Word-Line Biasing Control Scheme for Leakage Reduction of DRAM

CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction

10T SRAM Using Half- V} Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage

Low-Voltage CMOS Differential Logic Style With Supply Voltage Approaching Device Threshold

Conditional-capture flip-flop for statistical power reduction

High-Speed Rail-to-Rail Class-AB Buffer Amplifier with Compact, Adaptive Biasing for FPD Applications

Low-Voltage Bootstrapped CMOS Drivers With Efficient Conditional Bootstrapping

A line inversion-based stepwise data driving for low-power mobile TFT-LCDs

Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation

A 6 Gbps/pin Low‐Power Half‐Duplex Active Cross‐Coupled LVDS Transceiver with Switched Termination

A DFE Receiver With Equalized VREF for Multidrop Single-Ended Signaling

CMOS Charge Pump With No Reversion Loss and Enhanced Drivability

Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations

10.4 A 5.8Gb/s adaptive integrating duobinary-based DFE receiver for multi-drop memory interface

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