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A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors

IEEE journal of solid-state circuits, 2020-10, Vol.55 (10), p.2790-2801

2020

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A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips

IEEE journal of solid-state circuits, 2021-09, Vol.56 (9), p.2817-2831

2021

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Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips

IEEE journal of solid-state circuits, 2022-02, Vol.57 (2), p.609-624

2022

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A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips

IEEE journal of solid-state circuits, 2023-03, Vol.58 (3), p.877-892

2023

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An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update

IEEE journal of solid-state circuits, 2024-05, Vol.59 (5), p.1612-1627

2024

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An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips

IEEE journal of solid-state circuits, 2024-07, Vol.59 (7), p.2297-2309

2024

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A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips

IEEE journal of solid-state circuits, 2024-01, Vol.59 (1), p.196-207

2024

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A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices

2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023, p.126-128

2023

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8-bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips

IEEE transactions on circuits and systems. II, Express briefs, 2024-04, Vol.71 (4), p.1-1

2024

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34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.568-570

2024

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A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.1-3

2022

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RRAM-based Spiking Nonvolatile Computing-In-Memory Processing Engine with Precision-Configurable In Situ Nonlinear Activation

2019 Symposium on VLSI Technology, 2019, p.T86-T87

2019

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A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training

2020 57th ACM/IEEE Design Automation Conference (DAC), 2020, p.1-6

2020

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MSig-BFT: A Witness-Based Consensus Algorithm for Private Blockchains

2018 IEEE 24th International Conference on Parallel and Distributed Systems (ICPADS), 2018, p.992-997

2018

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16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.250-252

2021

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Cross-Layer Optimizations in Solid-State Drives

IEEE embedded systems letters, 2011-12, Vol.3 (4), p.109-112

2011

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Circuit Design Challenges in Computing-in-Memory for AI Edge Devices

2019 IEEE 13th International Conference on ASIC (ASICON), 2019, p.1-4

2019

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A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme

2017 IEEE International Electron Devices Meeting (IEDM), 2017, p.28.2.1-28.2.4

2017

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A study on modular design representation

2007 IEEE International Conference on Industrial Engineering and Engineering Management, 2007, p.1327-1331

2007

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15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.246-248

2020

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A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors

2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2019, p.217-218

2019

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15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.240-242

2020

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A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2021, p.1-3

2021

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BEOL-Compatible Multiple Metal-Ferroelectric-Metal (m-MFM) FETs Designed for Low Voltage (2.5 V), High Density, and Excellent Reliability

2020 IEEE International Electron Devices Meeting (IEDM), 2020, p.4.6.1-4.6.4

2020

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An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips

IEEE journal of solid-state circuits, 2024-10, p.1-13

2024

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A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips

An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update

An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips

A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips

A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices

8-bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips

34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices

A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices

RRAM-based Spiking Nonvolatile Computing-In-Memory Processing Engine with Precision-Configurable In Situ Nonlinear Activation

A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training

MSig-BFT: A Witness-Based Consensus Algorithm for Private Blockchains

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

Cross-Layer Optimizations in Solid-State Drives

Circuit Design Challenges in Computing-in-Memory for AI Edge Devices

A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme

A study on modular design representation

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips

A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration

BEOL-Compatible Multiple Metal-Ferroelectric-Metal (m-MFM) FETs Designed for Low Voltage (2.5 V), High Density, and Excellent Reliability

An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips

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