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Transactional WaveCache: Towards Speculative and Out-of-Order DataFlow Execution of Memory Operations

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.183-190

2008

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Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.159-166

2008

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Measuring Operating System Overhead on CMT Processors

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.133-140

2008

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A Segmented Bloom Filter Algorithm for Efficient Predictors

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.123-130

2008

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Processing Neocognitron of Face Recognition on High Performance Environment Based on GPU with CUDA Architecture

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.81-88

2008

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An Optimization Mechanism Intended for Two-Level Cache Hierarchy to Improve Energy and Performance Using the NSGAII Algorithm

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.19-26

2008

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On Simulated Annealing for the Scheduling of Parallel Applications

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.29-36

2008

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A High Performance Massively Parallel Approach for Real Time Deformable Body Physics Simulation

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.45-52

2008

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Parallel Verified Linear System Solver for Uncertain Input Data

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.89-96

2008

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Applying Virtualization and System Management in a Cluster to Implement an Automated Emulation Testbed for Grid Applications

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.97-104

2008

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Controlling Processes Reassignment in BSP Applications

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.37-44

2008

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A Methodology for Developing High Fidelity Communication Models for Large-Scale Applications Targeted on Multicore Systems

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.55-62

2008

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Software Synthesis for Hard Real-Time Embedded Systems with Energy Constraints

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.115-122

2008

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Accurate and Low-Overhead Dynamic Detection and Prediction of Program Phases Using Branch Signatures

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.3-10

2008

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ORBIT: Effective Issue Queue Soft-Error Vulnerability Mitigation on Simultaneous Multithreaded Architectures Using Operand Readiness-Based Instruction Dispatch

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.71-78

2008

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Aggressive Scheduling and Speculation in Multithreaded Architectures: Is it Worth its Salt?

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.11-18

2008

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Selection of the Register File Size and the Resource Allocation Policy on SMT Processors

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.63-70

2008

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Hiding Communication Delays in Clustered Microarchitectures

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.107-114

2008

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A Software Transactional Memory System for an Asymmetric Processor Architecture

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.175-182

2008

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Performance Sensitivity of NUCA Caches to On-Chip Network Parameters

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.167-174

2008

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A Reconfigurable Run-Time System for Filter-Stream Applications

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.149-156

2008

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Aspect-Based Patterns for Grid Programming

2008 20th International Symposium on Computer Architecture and High Performance Computing, 2008, p.141-148

2008

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The Case for VM-Based Cloudlets in Mobile Computing

IEEE pervasive computing, 2009-10, Vol.8 (4), p.14-23

2009

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Hybrid Cooperative Positioning Based on Distributed Belief Propagation

IEEE journal on selected areas in communications, 2011-12, Vol.29 (10), p.1948-1958

2011

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Fast Smoke Detection for Video Surveillance Using CUDA

IEEE transactions on industrial informatics, 2018-02, Vol.14 (2), p.725-733

2018

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Transactional WaveCache: Towards Speculative and Out-of-Order DataFlow Execution of Memory Operations

Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design

Measuring Operating System Overhead on CMT Processors

A Segmented Bloom Filter Algorithm for Efficient Predictors

Processing Neocognitron of Face Recognition on High Performance Environment Based on GPU with CUDA Architecture

An Optimization Mechanism Intended for Two-Level Cache Hierarchy to Improve Energy and Performance Using the NSGAII Algorithm

On Simulated Annealing for the Scheduling of Parallel Applications

A High Performance Massively Parallel Approach for Real Time Deformable Body Physics Simulation

Parallel Verified Linear System Solver for Uncertain Input Data

Applying Virtualization and System Management in a Cluster to Implement an Automated Emulation Testbed for Grid Applications

Controlling Processes Reassignment in BSP Applications

A Methodology for Developing High Fidelity Communication Models for Large-Scale Applications Targeted on Multicore Systems

Software Synthesis for Hard Real-Time Embedded Systems with Energy Constraints

Accurate and Low-Overhead Dynamic Detection and Prediction of Program Phases Using Branch Signatures

ORBIT: Effective Issue Queue Soft-Error Vulnerability Mitigation on Simultaneous Multithreaded Architectures Using Operand Readiness-Based Instruction Dispatch

Aggressive Scheduling and Speculation in Multithreaded Architectures: Is it Worth its Salt?

Selection of the Register File Size and the Resource Allocation Policy on SMT Processors

Hiding Communication Delays in Clustered Microarchitectures

A Software Transactional Memory System for an Asymmetric Processor Architecture

Performance Sensitivity of NUCA Caches to On-Chip Network Parameters

A Reconfigurable Run-Time System for Filter-Stream Applications

Aspect-Based Patterns for Grid Programming

The Case for VM-Based Cloudlets in Mobile Computing

Hybrid Cooperative Positioning Based on Distributed Belief Propagation

Fast Smoke Detection for Video Surveillance Using CUDA

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