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Performing Machine Learning Based Outlier Detection for Automotive Grade Products

2023 IEEE International Reliability Physics Symposium (IRPS), 2023, p.1-5

2023

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Characteristics of MOS capacitors of BF2 or B implanted polysilicon gate with and without POCl3 co-doped

IEEE electron device letters, 1993-05, Vol.14 (5), p.222-224

1993

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High-performance salicide shallow-junction CMOS devices for submicrometer VLSI application in twin-tub VI

IEEE transactions on electron devices, 1989-11, Vol.36 (11), p.2530-2536

1989

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An analog/digital BCDMOS technology with dielectric isolation-devices and processes

IEEE transactions on electron devices, 1988-02, Vol.35 (2), p.230-239

1988

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A folded extended window MOSFET for ULSI applications

IEEE electron device letters, 1988-08, Vol.9 (8), p.388-390

1988

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Using oxide sidewall taper to improve breakdown voltage in planar junction of DMOS devices by a simple process

Electronics letters, 1987, Vol.23 (8), p.407-408

1987

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The anomalous threshold voltage shift of N- and P-MOSFET under flow and reflow of BPSG film with RTA and/or furnace

IEEE transactions on electron devices, 1994-03, Vol.41 (3), p.458-460

1994

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Process limitation and device design tradeoffs of self-aligned TiSi/sub 2/ junction formation in submicrometer CMOS devices

IEEE transactions on electron devices, 1991-02, Vol.38 (2), p.246-254

1991

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The origins of the performance degradation of implanted P+ polysilicon gated P-channel MOSFET with/without rapid thermal annealing

IEEE transactions on electron devices, 1994-05, Vol.41 (5), p.692-697

1994

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Coplanar waveguide-fed uniplanar bow-tie antenna

IEEE transactions on antennas and propagation, 1997-02, Vol.45 (2), p.305-306

1997

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Analysis and design of broadside-coupled striplines-fed bow-tie antennas

IEEE transactions on antennas and propagation, 1998-03, Vol.46 (3), p.459-460

1998

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A new and improved structure of polysilicon resistor for subquarter micrometer CMOS device applications

IEEE transactions on electron devices, 2003-02, Vol.50 (2), p.516-518

2003

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The origins of the performance degradation of implanted p(+) polysilicon gated p-channel MOSFET with/without rapid thermalannealing

IEEE transactions on electron devices, 1994-05, Vol.41 (5), p.692-697

1994

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Characteristics of MOS capacitors of BF(2) or B implantedpolysilicon gate with and without POCl(3) co-doped

IEEE electron device letters, 1993-05, Vol.14 (5), p.222-224

1993

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Camera calibration by vanishing lines for 3-D computer vision

IEEE transactions on pattern analysis and machine intelligence, 1991-04, Vol.13 (4), p.370-376

1991

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Process limitation and device design tradeoffs of self-aligned TiSi(2) junction formation in submicrometer CMOS devices

IEEE transactions on electron devices, 1991-02, Vol.38 (2), p.246-254

1991

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Process limitation and device design tradeoffs of self-aligned TiSi2 junction formation in submicrometer CMOS devices

IEEE transactions on electron devices, 1991-02, Vol.38 (2), p.246-254

1991

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Process limitation and device design tradeoffs of self-aligned TiSi sub(2) junction formation in submicrometer CMOS devices

IEEE transactions on electron devices, 1991-01, Vol.38 (2), p.246-254

1991

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High-performance silicide shallow-junction CMOS devices for submicrometer VLSI application in twin-tub VI

IEEE transactions on electron devices, 1989-01, Vol.36 (11), p.2530-2536

1989

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Limitations of rapid thermal processing on ultra-shallow junctions for sub-0.25 mu m MOSFETs

1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers, 1993, p.20-23

1993

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Overview for 300 mm foundry manufacturing

Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461), 2001, p.I-III

Nun-Sian Tsai

2001

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Underfill characterization for low-k dielectric / Cu interconnect IC flip-chip package reliability

2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546), 2004, Vol.1, p.767-769 Vol.1

2004

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Cavity-down thermal-enhanced package reliability evaluation for low-k dielectric/Cu interconnects IC

2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546), 2004, Vol.2, p.1191-1193 Vol.2

2004

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Dispersion and leakage characteristics of coplanar waveguides

IEEE transactions on microwave theory and techniques, 1992-10, Vol.40 (10), p.1970-1973

1992

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Layer tungsten and its applications for VLSI interconnects

Technical Digest., International Electron Devices Meeting, 1988, p.462-465

1988

Volltextzugriff (PDF)

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Performing Machine Learning Based Outlier Detection for Automotive Grade Products

Characteristics of MOS capacitors of BF2 or B implanted polysilicon gate with and without POCl3 co-doped

High-performance salicide shallow-junction CMOS devices for submicrometer VLSI application in twin-tub VI

An analog/digital BCDMOS technology with dielectric isolation-devices and processes

A folded extended window MOSFET for ULSI applications

Using oxide sidewall taper to improve breakdown voltage in planar junction of DMOS devices by a simple process

The anomalous threshold voltage shift of N- and P-MOSFET under flow and reflow of BPSG film with RTA and/or furnace

Process limitation and device design tradeoffs of self-aligned TiSi/sub 2/ junction formation in submicrometer CMOS devices

The origins of the performance degradation of implanted P+ polysilicon gated P-channel MOSFET with/without rapid thermal annealing

Coplanar waveguide-fed uniplanar bow-tie antenna

Analysis and design of broadside-coupled striplines-fed bow-tie antennas

A new and improved structure of polysilicon resistor for subquarter micrometer CMOS device applications

The origins of the performance degradation of implanted p(+) polysilicon gated p-channel MOSFET with/without rapid thermalannealing

Characteristics of MOS capacitors of BF(2) or B implantedpolysilicon gate with and without POCl(3) co-doped

Camera calibration by vanishing lines for 3-D computer vision

Process limitation and device design tradeoffs of self-aligned TiSi(2) junction formation in submicrometer CMOS devices

Process limitation and device design tradeoffs of self-aligned TiSi2 junction formation in submicrometer CMOS devices

Process limitation and device design tradeoffs of self-aligned TiSi sub(2) junction formation in submicrometer CMOS devices

High-performance silicide shallow-junction CMOS devices for submicrometer VLSI application in twin-tub VI

Limitations of rapid thermal processing on ultra-shallow junctions for sub-0.25 mu m MOSFETs

Overview for 300 mm foundry manufacturing

Underfill characterization for low-k dielectric / Cu interconnect IC flip-chip package reliability

Cavity-down thermal-enhanced package reliability evaluation for low-k dielectric/Cu interconnects IC

Dispersion and leakage characteristics of coplanar waveguides

Layer tungsten and its applications for VLSI interconnects

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