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Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics

IEEE electron device letters, 2003-02, Vol.24 (2), p.87-89

2003

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Challenges in the characterization and modeling of BTI induced variability in metal gate / High-k CMOS technologies

2013 IEEE International Reliability Physics Symposium (IRPS), 2013, p.2D.4.1-2D.4.6

2013

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Voltage Ramp Stress for Bias Temperature Instability Testing of Metal-Gate/High- k Stacks

IEEE electron device letters, 2009-12, Vol.30 (12), p.1347-1349

2009

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Voltage Ramp Stress for Hot-Carrier Screening of Scaled CMOS Devices

IEEE electron device letters, 2012-06, Vol.33 (6), p.749-751

2012

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On the thermal stability of atomic layer deposited TiN as gate electrode in MOS devices

IEEE electron device letters, 2003-09, Vol.24 (9), p.550-552

2003

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A Study of Relaxation Current in High- $kappa$ Dielectric Stacks

IEEE transactions on electron devices, 2004-03, Vol.51 (3), p.402-408

2004

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Impact of failure criteria on the reliability prediction of CMOS devices with ultrathin gate oxides based on voltage ramp stress

IEEE electron device letters, 2006-07, Vol.27 (7), p.609-611

2006

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Bottom-up methodology for predictive simulations of self-heating in aggressively scaled process technologies

2018 IEEE International Reliability Physics Symposium (IRPS), 2018, p.6F.6-1-6F.6-7

2018

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Impact of RTN on stochastic BTI degradation in scaled metal gate/high-k CMOS technologies

2015 IEEE International Reliability Physics Symposium, 2015, p.3B.3.1-3B.3.6

Kerber, A.

2015

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From wafer-level gate-oxide reliability towards ESD failures in advanced CMOS technologies

IEEE transactions on electron devices, 2006-04, Vol.53 (4), p.917-920

2006

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PBTI relaxation dynamics after AC vs. DC stress in high-k/metal gate stacks

2010 IEEE International Reliability Physics Symposium, 2010, p.50-54

2010

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Self-heating impact on TDDB in bulk FinFET devices: Uniform vs Non-uniform Stress

2016 IEEE International Integrated Reliability Workshop (IIRW), 2016, p.45-48

2016

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Impact of charge trapping on the voltage acceleration of TDDB in metal gate/high-k n-channel MOSFETs

2010 IEEE International Reliability Physics Symposium, 2010, p.369-372

2010

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PBTI under dynamic stress: From a single defect point of view

2011 International Reliability Physics Symposium, 2011, p.4A.3.1-4A.3.9

2011

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Application of CVS and VRS method for correlation of logic CMOS wear out to discrete device degradation based on ring oscillator circuits

2016 IEEE Symposium on VLSI Technology, 2016, p.1-2

2016

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Correlation between stress-induced leakage current (SILC) and the HfO2 bulk trap density in a SiO2/HfO2 stack

2004

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Accurate model for time-dependent dielectric breakdown of high-k metal gate stacks

2009 IEEE International Reliability Physics Symposium, 2009, p.523-530

2009

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Fast wafer level data acquisition for reliability characterization of sub-100 nm CMOS technologies

IEEE International Integrated Reliability Workshop Final Report, 2004, 2004, p.41-45

2004

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Correlation of BTI induced device parameter degradation and variation in scaled Metal Gate / High-k CMOS technologies

2014 IEEE International Reliability Physics Symposium, 2014, p.6A.6.1-6A.6.6

2014

Volltextzugriff (PDF)

Fast characterization of the Static Noise Margin degradation of cross-coupled inverters and correlation to BTI instabilities in MG/HK devices

2011 International Reliability Physics Symposium, 2011, p.2B.3.1-2B.3.6

2011

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Ambient temperature and layout impact on self-heating characterization in FinFET devices

2018 IEEE International Reliability Physics Symposium (IRPS), 2018, p.6E.2-1-6E.2-5

2018

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Stress-induced leakage current and defect generation in nFETs with HfO2/TiN gate stacks during positive-bias temperature stress

2009 IEEE International Reliability Physics Symposium, 2009, p.486-492

2009

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Impact of AC voltage stress on core NMOSFETs TDDB in FinFET and planar technologies

2017 IEEE International Reliability Physics Symposium (IRPS), 2017, p.DG-10.1-DG-10.5

2017

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A Fast Four-Point Sense Methodology for Extraction of Circuit-Relevant Degradation Parameters

IEEE electron device letters, 2010-09, Vol.31 (9), p.912-914

2010

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Self-heating measurement methodologies and their assessment on bulk FinFET devices

2017 IEEE International Integrated Reliability Workshop (IIRW), 2017, p.1-4

2017

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Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics

Challenges in the characterization and modeling of BTI induced variability in metal gate / High-k CMOS technologies

Voltage Ramp Stress for Bias Temperature Instability Testing of Metal-Gate/High- k Stacks

Voltage Ramp Stress for Hot-Carrier Screening of Scaled CMOS Devices

On the thermal stability of atomic layer deposited TiN as gate electrode in MOS devices

A Study of Relaxation Current in High- $kappa$ Dielectric Stacks

Impact of failure criteria on the reliability prediction of CMOS devices with ultrathin gate oxides based on voltage ramp stress

Bottom-up methodology for predictive simulations of self-heating in aggressively scaled process technologies

Impact of RTN on stochastic BTI degradation in scaled metal gate/high-k CMOS technologies

From wafer-level gate-oxide reliability towards ESD failures in advanced CMOS technologies

PBTI relaxation dynamics after AC vs. DC stress in high-k/metal gate stacks

Self-heating impact on TDDB in bulk FinFET devices: Uniform vs Non-uniform Stress

Impact of charge trapping on the voltage acceleration of TDDB in metal gate/high-k n-channel MOSFETs

PBTI under dynamic stress: From a single defect point of view

Application of CVS and VRS method for correlation of logic CMOS wear out to discrete device degradation based on ring oscillator circuits

Correlation between stress-induced leakage current (SILC) and the HfO2 bulk trap density in a SiO2/HfO2 stack

Accurate model for time-dependent dielectric breakdown of high-k metal gate stacks

Fast wafer level data acquisition for reliability characterization of sub-100 nm CMOS technologies

Correlation of BTI induced device parameter degradation and variation in scaled Metal Gate / High-k CMOS technologies

Fast characterization of the Static Noise Margin degradation of cross-coupled inverters and correlation to BTI instabilities in MG/HK devices

Ambient temperature and layout impact on self-heating characterization in FinFET devices

Stress-induced leakage current and defect generation in nFETs with HfO2/TiN gate stacks during positive-bias temperature stress

Impact of AC voltage stress on core NMOSFETs TDDB in FinFET and planar technologies

A Fast Four-Point Sense Methodology for Extraction of Circuit-Relevant Degradation Parameters

Self-heating measurement methodologies and their assessment on bulk FinFET devices

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