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A Survey on Protograph LDPC Codes and Their Applications

IEEE Communications surveys and tutorials, 2015-01, Vol.17 (4), p.1989-2016

2015

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Rate-Compatible Root-Protograph LDPC Codes for Quasi-Static Fading Relay Channels

IEEE transactions on vehicular technology, 2016-04, Vol.65 (4), p.2741-2747

2016

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Finite-length extrinsic information transfer analysis and design of protograph low-density parity-check codes for ultra-high-density magnetic recording channels

IET communications, 2016-07, Vol.10 (11), p.1303-1311

2016

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Fast full search equivalent encoding algorithms for image compression using vector quantization

IEEE transactions on image processing, 1992-07, Vol.1 (3), p.413-416

1992

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Highly scalable on-axis confined cell structure for high density PRAM beyond 256Mb

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005, 2005, p.96-97

2005

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Simulation and modeling of wafer level silicon-base spiral inductor

2012 13th International Conference on Electronic Packaging Technology & High Density Packaging, 2012, p.29-31

2012

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Project-Based Learning for AI-enabling Mechatronic Design Course

2024 International Conference on Advanced Robotics and Mechatronics (ICARM), 2024, p.419-424

2024

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Structural and compositional optimization of advanced fan-in WLCSPs base on FEA simulation

2012 13th International Conference on Electronic Packaging Technology & High Density Packaging, 2012, p.25-28

2012

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Optimization of the Microwave Induced Plasma system for failure analysis in integrated circuit packaging

2010 11th International Conference on Electronic Packaging Technology & High Density Packaging, 2010, p.1034-1038

2010

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A novel wafer level packaging for white light LED

2013 14th International Conference on Electronic Packaging Technology, 2013, p.1170-1174

2013

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Efficient multiway graph partitioning method for fault section estimation in large-scale power networks

IEE proceedings. Generation, transmission, and distribution, 2002-05, Vol.149 (3), p.289

2002

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Fabrication and measurement of Si-based inductors integrated in WLP

2013 14th International Conference on Electronic Packaging Technology, 2013, p.27-29

2013

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A study of novel wafer level LED package based on TSV technology

2012 13th International Conference on Electronic Packaging Technology & High Density Packaging, 2012, p.52-55

2012

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Efficient implementation of a submodel for composite materials to be combined with the FDTD-algorithm

IEEE transactions on magnetics, 1994-09, Vol.30 (5), p.3188-3191

1994

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A new type of wafer level package based on silicon substrate

2013 14th International Conference on Electronic Packaging Technology, 2013, p.76-78

2013

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The investigation of high temperature joint generated by low temperature process

2010 11th International Conference on Electronic Packaging Technology & High Density Packaging, 2010, p.271-274

2010

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SCATOMi: scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture

Proceedings 21st International Conference on Computer Design, 2003, p.419-425

2003

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Microwave Induced Plasma decapsulation of thermally stressed multi-tier copper wire bonded IC packages

2013 14th International Conference on Electronic Packaging Technology, 2013, p.981-986

2013

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Development of temperature-stable thick-film dielectrics. III. Role of glass on the microstructure evolution of a thick-film dielectric

IEEE transactions on components, hybrids, and manufacturing technology, 1991-09, Vol.14 (3), p.645-649

1991

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Information, error, and imaging in deadtime-perturbed doubly stochastic Poisson counting systems

IEEE journal of quantum electronics, 1978-12, Vol.14 (12), p.993-1003

1978

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Solder bumps layout design and reliability enhancement of wafer level packaging

Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003, 2003, p.56-64

2003

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Unsupervised texture segmentation using grey levels rank-vectors

Proceedings of Third International Conference on Signal Processing (ICSP'96), 1996, Vol.2, p.1273-1276 vol.2

1996

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Synthesis and optimization of interface hardware between IP's operating at different clock frequencies

Proceedings 2000 International Conference on Computer Design, 2000, p.519-524

2000

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Challenges and approaches of TSV thin die stacking on organic substrate

2011 IEEE 13th Electronics Packaging Technology Conference, 2011, p.455-461

2011

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Optimum doping profile of power MOSFET epitaxial layer

IEEE transactions on electron devices, 1982-06, Vol.29 (6), p.985-987

1982

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A Survey on Protograph LDPC Codes and Their Applications

Rate-Compatible Root-Protograph LDPC Codes for Quasi-Static Fading Relay Channels

Finite-length extrinsic information transfer analysis and design of protograph low-density parity-check codes for ultra-high-density magnetic recording channels

Fast full search equivalent encoding algorithms for image compression using vector quantization

Highly scalable on-axis confined cell structure for high density PRAM beyond 256Mb

Simulation and modeling of wafer level silicon-base spiral inductor

Project-Based Learning for AI-enabling Mechatronic Design Course

Structural and compositional optimization of advanced fan-in WLCSPs base on FEA simulation

Optimization of the Microwave Induced Plasma system for failure analysis in integrated circuit packaging

A novel wafer level packaging for white light LED

Efficient multiway graph partitioning method for fault section estimation in large-scale power networks

Fabrication and measurement of Si-based inductors integrated in WLP

A study of novel wafer level LED package based on TSV technology

Efficient implementation of a submodel for composite materials to be combined with the FDTD-algorithm

A new type of wafer level package based on silicon substrate

The investigation of high temperature joint generated by low temperature process

SCATOMi: scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture

Microwave Induced Plasma decapsulation of thermally stressed multi-tier copper wire bonded IC packages

Development of temperature-stable thick-film dielectrics. III. Role of glass on the microstructure evolution of a thick-film dielectric

Information, error, and imaging in deadtime-perturbed doubly stochastic Poisson counting systems

Solder bumps layout design and reliability enhancement of wafer level packaging

Unsupervised texture segmentation using grey levels rank-vectors

Synthesis and optimization of interface hardware between IP's operating at different clock frequencies

Challenges and approaches of TSV thin die stacking on organic substrate

Optimum doping profile of power MOSFET epitaxial layer

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