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Degradation of Memory Retention Characteristics in DRAM Chip by Si Thinning for 3-D Integration

IEEE electron device letters, 2013-08, Vol.34 (8), p.1038-1040

2013

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Impact of Cu Contamination on Memory Retention Characteristics in Thinned DRAM Chip for 3-D Integration

IEEE electron device letters, 2012-09, Vol.33 (9), p.1297-1299

2012

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A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control

IEEE journal of solid-state circuits, 2009-12, Vol.44 (12), p.3547-3559

2009

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Impacts of 3-D Integration Processes on Memory Retention Characteristics in Thinned DRAM Chip for High-Reliable 3-D DRAM

IEEE transactions on electron devices, 2014-02, Vol.61 (2), p.379-385

2014

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A 56-Gb/s Wireline Transceiver in 20nm CMOS

2015 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 2015, p.1-4

2015

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Impacts of Cu contamination in 3D integration process on memory retention characteristics in thinned DRAM chip

2014 IEEE International Reliability Physics Symposium, 2014, p.3E.4.1-3E.4.6

2014

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22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015, p.1-3

2015

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3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS

2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, p.64-65

2016

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A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.188-189,189a

2009

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A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel

2011 IEEE International Solid-State Circuits Conference, 2011, p.346-348

2011

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A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.442-443

2007

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24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR

2016 Optical Fiber Communications Conference and Exhibition (OFC), 2016, p.1-3

2016

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25.78-Gb/s VCSEL-based optical transceiver with retimer-embedded driver and receiver ICs

2015 Optical Fiber Communications Conference and Exhibition (OFC), 2015, p.1-3

2015

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A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS

2014 Symposium on VLSI Circuits Digest of Technical Papers, 2014, p.1-2

2014

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A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016, p.1-2

2016

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22.7 425.78Gb/s retimer ICs for optical links in 0.13 mu m SiGe BiCMOS

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015-02, p.1-3

2015

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Design Consideration of 6.25 Gbps Signaling for High-Performance Server

2007 Asia and South Pacific Design Automation Conference, 2007, p.854-857

2007

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Gain-phase co-equalization for widely-used high-speed cables

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005, 2005, p.194-197

2005

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A 4-channel 3.125Gb/s/ch CMOS transceiver with 30dB equalization

2003

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Degradation of Memory Retention Characteristics in DRAM Chip by Si Thinning for 3-D Integration

Impact of Cu Contamination on Memory Retention Characteristics in Thinned DRAM Chip for 3-D Integration

A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control

Impacts of 3-D Integration Processes on Memory Retention Characteristics in Thinned DRAM Chip for High-Reliable 3-D DRAM

A 56-Gb/s Wireline Transceiver in 20nm CMOS

Impacts of Cu contamination in 3D integration process on memory retention characteristics in thinned DRAM chip

22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS

A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control

A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel

A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer

24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR

25.78-Gb/s VCSEL-based optical transceiver with retimer-embedded driver and receiver ICs

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS

22.7 425.78Gb/s retimer ICs for optical links in 0.13 mu m SiGe BiCMOS

Design Consideration of 6.25 Gbps Signaling for High-Performance Server

Gain-phase co-equalization for widely-used high-speed cables

A 4-channel 3.125Gb/s/ch CMOS transceiver with 30dB equalization

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