UB Paderborn / Katalog / Suche / in CDI

Securing a RISC-V architecture: A dynamic approach

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023, p.1-5

2023

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A new orthogonal online digital calibration for time-interleaved analog-to-digital converters

2008 IEEE International Symposium on Circuits and Systems, 2008, p.576-579

2008

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Softcore Processor Optimization According to Real-Application Requirements

IEEE embedded systems letters, 2013-03, Vol.5 (1), p.4-7

2013

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Study and analysis of a new implementation of a mixed-signal cartesian feedback for a low power zero-IF WCDMA transmitter

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS), 2013, p.1-4

2013

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Zebra: Building Efficient Network Message Parsers for Embedded Systems

IEEE embedded systems letters, 2012-09, Vol.4 (3), p.69-72

2012

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Mixed Cartesian feedback for Zero-IF WCDMA transmitter

2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS), 2011, p.1-4

2011

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Design and Implementation of a Reconfigurable Decimation and Channel Selection Filter for GSM and UMTS Radio Standards

2009 IEEE Wireless Communications and Networking Conference, 2009, p.1-6

2009

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A reconfigurable Crypto Sub System for the Software Communication Architecture

MILCOM 2009 - 2009 IEEE Military Communications Conference, 2009, p.1-7

2009

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FPGA prototyping of an ASIP LDPC decoder for the DVB-T2 standard

Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012, p.1-2

2012

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High-level synthesis assisted rapid prototyping for digital signal processing

Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004, 2004, p.746-749

2004

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Hardware virtual components compliant with communication system standards

8th Euromicro Conference on Digital System Design (DSD'05), 2005, p.88-95

2005

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Design of an ASIP LDPC Decoder Compliant with Digital Communication Standards

2012 IEEE Workshop on Signal Processing Systems, 2012, p.19-24

2012

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High-level synthesis for the design of FPGA-based signal processing systems

2009 International Symposium on Systems, Architectures, Modeling, and Simulation, 2009, p.25-32

2009

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Assertion support in high-level synthesis design flow

FDL 2011 Proceedings, 2011, p.1-8

2011

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Spatial downsizing impact in the transrating tradeoff for content/context awareness in media network

2012 International Conference on Telecommunications and Multimedia (TEMU), 2012, p.158-162

2012

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A generic video adaptation FPGA implementation towards content- and context-awareness in future networks

Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012, p.1-7

2012

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Performances analysis and evaluation of Xenomai with a H.264/AVC decoder

ICM 2011 Proceeding, 2011, p.1-4

2011

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Using Digital Signal Processor singularities to minimize ROM based controller area

Proceedings of the 8th IEEE International NEWCAS Conference 2010, 2010, p.29-32

2010

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A generic video adaptation framework towards content-and context-awareness in future networks

2012 Proceedings of the 20th European Signal Processing Conference (EUSIPCO), 2012, p.2218-2222

2012

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Design of a mixed-signal Cartesian Feedback loop for a low power zero-IF WCDMA transmitter

2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS), 2012, p.1-4

2012

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A system aproach for reducing power consumption of multimedia devices with a low QoE impact

2011 18th IEEE International Conference on Electronics, Circuits, and Systems, 2011, p.5-8

2011

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Power consumption estimation models for FIR decimation filters in multi-standard receivers

2011 IEEE GCC Conference and Exhibition (GCC), 2011, p.617-620

2011

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IP Generation Targeting Multiple Bit-Width Standards

2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006, p.784-787

2006

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New digital predistortion design based on mixed-signal cartesian feedback training for 3G homodyne transmitter

10th IEEE International NEWCAS Conference, 2012, p.93-96

2012

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Evaluation of FIR filters implementations for low power multistandard receivers

5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2010, p.1-5

2010

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Securing a RISC-V architecture: A dynamic approach

A new orthogonal online digital calibration for time-interleaved analog-to-digital converters

Softcore Processor Optimization According to Real-Application Requirements

Study and analysis of a new implementation of a mixed-signal cartesian feedback for a low power zero-IF WCDMA transmitter

Zebra: Building Efficient Network Message Parsers for Embedded Systems

Mixed Cartesian feedback for Zero-IF WCDMA transmitter

Design and Implementation of a Reconfigurable Decimation and Channel Selection Filter for GSM and UMTS Radio Standards

A reconfigurable Crypto Sub System for the Software Communication Architecture

FPGA prototyping of an ASIP LDPC decoder for the DVB-T2 standard

High-level synthesis assisted rapid prototyping for digital signal processing

Hardware virtual components compliant with communication system standards

Design of an ASIP LDPC Decoder Compliant with Digital Communication Standards

High-level synthesis for the design of FPGA-based signal processing systems

Assertion support in high-level synthesis design flow

Spatial downsizing impact in the transrating tradeoff for content/context awareness in media network

A generic video adaptation FPGA implementation towards content- and context-awareness in future networks

Performances analysis and evaluation of Xenomai with a H.264/AVC decoder

Using Digital Signal Processor singularities to minimize ROM based controller area

A generic video adaptation framework towards content-and context-awareness in future networks

Design of a mixed-signal Cartesian Feedback loop for a low power zero-IF WCDMA transmitter

A system aproach for reducing power consumption of multimedia devices with a low QoE impact

Power consumption estimation models for FIR decimation filters in multi-standard receivers

IP Generation Targeting Multiple Bit-Width Standards

New digital predistortion design based on mixed-signal cartesian feedback training for 3G homodyne transmitter

Evaluation of FIR filters implementations for low power multistandard receivers

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