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A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology

2019 IEEE Hot Chips 31 Symposium (HCS), 2019, p.1-24

2019

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A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm

2019 Symposium on VLSI Circuits, 2019, p.C300-C301

2019

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0.3% efficiency improvement for n-PERT solar cells with illuminated hydrogenation process

AIP Conference Proceedings, 2022, Vol.2487 (1)

2022

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A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

IEEE journal of solid-state circuits, 2020-04, Vol.55 (4), p.920-932

2020

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A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators

IEEE journal of solid-state circuits, 2005-12, Vol.40 (12), p.2398-2407

2005

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10-kV Ga 2 O 3 Charge-Balance Schottky Rectifier Operational at 200 °C

IEEE electron device letters, 2023-08, Vol.44 (8), p.1268-1271

2023

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10 kV Ga2O3 Charge-Balance Schottky Rectifier Operational at 200 °C

IEEE electron device letters, 2023-06, Vol.44 (8), p.1-1

2023

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100 Gb/s (10/spl times/10 Gb/s) DWDM photonic integrated circuit transmitters and receivers

(CLEO). Conference on Lasers and Electro-Optics, 2005, 2005, Vol.1, p.585-587 Vol. 1

2005

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A 10b 170MS/s CMOS Pipelined ADC Featuring 84dB SFDR without Calibration

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers, 2006, p.226-227

2006

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128 channels of multi-gigasample-per-second waveform sampling and digitization in a 10 cm × 10 cm × 8 cm package

2012 18th IEEE-NPSS Real Time Conference, 2012, p.1-5

2012

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1310-nm Hybrid III-V/Si Fabry-Pérot Laser Based on Adhesive Bonding

IEEE photonics technology letters, 2011-12, Vol.23 (23), p.1781-1783

2011

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A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, p.466-467

2013

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The 1958 Viscount Nuffield paper. Report and discussion

Institution of Production Engineers Journal, 1959, Vol.38 (5), p.238

1959

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A 2.9ns random access cycle embedded DRAM with a destructive-read architecture

2002

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20 Years of Turbo Coding and Energy-Aware Design Guidelines for Energy-Constrained Wireless Applications

IEEE Communications surveys and tutorials, 2016, Vol.18 (1), p.8-28

2016

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2016 SMPTE Fellows

SMPTE motion imaging journal, 2016-10, Vol.125 (8), p.10-13

2016

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20x-Real time modeling and simulation of more electric aircraft thermally integrated electrical power systems

2016 International Conference on Electrical Systems for Aircraft, Railway, Ship Propulsion and Road Vehicles & International Transportation Electrification Conference (ESARS-ITEC), 2016, p.1-6

2016

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A 23 - 32 GHz LNA with Near 5 W Power Handling Capability Using 180 nm GaN HEMT Technology

2023 18th European Microwave Integrated Circuits Conference (EuMIC), 2023, p.1-4

2023

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A 256-Mcell Phase-Change Memory Chip Operating at 2 Bit/Cell

IEEE transactions on circuits and systems. I, Regular papers, 2013-06, Vol.60 (6), p.1521-1533

2013

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A 275-25-GHz tunerless waveguide receiver based on AIN-barrier SIS technology

IEEE transactions on microwave theory and techniques, 2007, Vol.55 (10), p.2086-2096

2007

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A 275-425-GHz Tunerless Waveguide Receiver Based on AlN-Barrier SIS Technology

IEEE transactions on microwave theory and techniques, 2007-10, Vol.55 (10), p.2086-2096

2007

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A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation

IEEE journal of solid-state circuits, 2016-02, Vol.51 (2), p.557-567

2016

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2D PIC-DSMC simulation of microscale breakdown after vacuum seal failure

2014 IEEE 41st International Conference on Plasma Sciences (ICOPS) held with 2014 IEEE International Conference on High-Power Particle Beams (BEAMS), 2014, p.1-1

2014

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3-D Scene Modelling from Multiple Images using Radial Basis Function Networks

2007 IEEE Workshop on Machine Learning for Signal Processing, 2007, p.105-110

2007

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3-dimensional display for clustered multi-relational parallel coordinates

Ninth International Conference on Information Visualisation (IV'05), 2005, p.188-193

2005

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A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm

0.3% efficiency improvement for n-PERT solar cells with illuminated hydrogenation process

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators

10-kV Ga 2 O 3 Charge-Balance Schottky Rectifier Operational at 200 °C

10 kV Ga2O3 Charge-Balance Schottky Rectifier Operational at 200 °C

100 Gb/s (10/spl times/10 Gb/s) DWDM photonic integrated circuit transmitters and receivers

A 10b 170MS/s CMOS Pipelined ADC Featuring 84dB SFDR without Calibration

128 channels of multi-gigasample-per-second waveform sampling and digitization in a 10 cm × 10 cm × 8 cm package

1310-nm Hybrid III-V/Si Fabry-Pérot Laser Based on Adhesive Bonding

A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction

The 1958 Viscount Nuffield paper. Report and discussion

A 2.9ns random access cycle embedded DRAM with a destructive-read architecture

20 Years of Turbo Coding and Energy-Aware Design Guidelines for Energy-Constrained Wireless Applications

2016 SMPTE Fellows

20x-Real time modeling and simulation of more electric aircraft thermally integrated electrical power systems

A 23 - 32 GHz LNA with Near 5 W Power Handling Capability Using 180 nm GaN HEMT Technology

A 256-Mcell Phase-Change Memory Chip Operating at 2 Bit/Cell

A 275-25-GHz tunerless waveguide receiver based on AIN-barrier SIS technology

A 275-425-GHz Tunerless Waveguide Receiver Based on AlN-Barrier SIS Technology

A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation

2D PIC-DSMC simulation of microscale breakdown after vacuum seal failure

3-D Scene Modelling from Multiple Images using Radial Basis Function Networks

3-dimensional display for clustered multi-relational parallel coordinates

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