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A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput
IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.150-162
2008
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End-to-End Deep Learning Architecture for Separating Maternal and Fetal ECGs Using W-Net
IEEE access, 2022, Vol.10, p.39782-39788
2022
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Reduction of Motion Artifacts From Remote Photoplethysmography Using Adaptive Noise Cancellation and Modified HSI Model
IEEE access, 2021, Vol.9, p.122655-122667
2021
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A 0.1-μm 1.8-V 256-Mb phase-change random access memory (PRAM) with 66-MHz synchronous burst-read operation
IEEE journal of solid-state circuits, 2007, Vol.42 (1), p.210-218
2007
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Elimination of ECG Artifacts from a Single-Channel EEG Using Sparse Derivative Method
2015 IEEE International Conference on Systems, Man, and Cybernetics, 2015, p.2384-2389
2015
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A CMOS image sensor (CIS) architecture with low power motion detection for portable security camera applications
IEEE transactions on consumer electronics, 2003-11, Vol.49 (4), p.1227-1233
2003
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A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM
IEEE journal of solid-state circuits, 2003-11, Vol.38 (11), p.1943-1951
2003
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Tracking driver's heart rate by continuous-wave Doppler radar
2016 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2016, Vol.2016, p.5417-5420
2016
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A 0.1- \mu} 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation
IEEE journal of solid-state circuits, 2007-01, Vol.42 (1), p.210-218
2007
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Blood Pressure Estimation using Pulse Transient Time Derived from Photoplethysmogram and Seismocardiogram in Smartphone
2022 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2022, p.587-590
2022
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A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW
2011 IEEE International Solid-State Circuits Conference, 2011, p.500-502
2011
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A Digitally Controlled Oscillator for Low Jitter All Digital Phase Locked Loops
2005 IEEE Asian Solid-State Circuits Conference, 2005, p.365-368
2005
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Excitation of surface plasmons in one-dimensional metal-dielectric photonic crystals
2007 Conference on Lasers and Electro-Optics - Pacific Rim, 2007, p.1-2
2007
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Eliminating cardiac electrical artifacts from cardiac autonomic nervous signals using a combination of empirical mode decomposition and independent component analysis
2013 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2013, Vol.2013, p.5841-5844
2013
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A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput
2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.472-616
2007
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A 0.1/spl mu/m 1.8V 256Mb 66MHz Synchronous Burst PRAM
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006, p.487-496
2006
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A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC, 2003, p.300-494 vol.1
2003
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A 200-mA Digital Low Drop-Out Regulator With Coarse-Fine Dual Loop in Mobile Application Processor
IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.64-76
2017
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Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM
IEEE journal of solid-state circuits, 2018-10, Vol.53 (10), p.2906-2916
2018
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Wideband Predistortion Technique With Dual-Parallel Schottky Diodes for Low Power RoF Systems
IEEE photonics technology letters, 2021-06, Vol.33 (11), p.569-572
2021
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Persistent Current Mode Operation of A 2G HTS Coil With A Flux Pump
IEEE transactions on applied superconductivity, 2016-06, Vol.26 (4), p.1-4
2016
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High Field-Effect Mobility Two-Channel InGaZnO Thin-Film Transistors for Low-Voltage Operation
IEEE transactions on electron devices, 2021-12, Vol.68 (12), p.6166-6170
2021
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Toward the Realization of Single-Photon Sources for Radiometry Applications at Room Temperature
IEEE transactions on instrumentation and measurement, 2023, Vol.72, p.1-7
2023
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Magnetization Loss of CORC With Various Configurations of 2G HTS Strands
IEEE transactions on applied superconductivity, 2021-08, Vol.31 (5), p.1-5
2021
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A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking
IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.197-209
2019
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