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Development, Implementation, and Characterization of a 64-Element Dual-Polarized Phased-Array Antenna Module for 28-GHz High-Speed Data Communications

IEEE transactions on microwave theory and techniques, 2019-07, Vol.67 (7), p.2975-2984

2019

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Physics-Based Via and Trace Models for Efficient Link Simulation on Multilayer Structures Up to 40 GHz

IEEE transactions on microwave theory and techniques, 2009-08, Vol.57 (8), p.2072-2083

2009

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A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

IEEE journal of solid-state circuits, 2006-12, Vol.41 (12), p.2885-2900

2006

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Energy-Aware Signal Integrity Analysis for High-Speed PCB Links

IEEE transactions on electromagnetic compatibility, 2015-10, Vol.57 (5), p.1226-1234

2015

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A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

IEEE journal of solid-state circuits, 2015-08, Vol.50 (8), p.1917-1931

2015

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Efficient Prediction of Equalization Effort and Channel Performance for PCB-Based Data Links

IEEE transactions on components, packaging, and manufacturing technology (2011), 2017-11, Vol.7 (11), p.1842-1851

2017

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A 24-Channel, 300 Gb/s, 8.2 pJ/bit, Full-Duplex Fiber-Coupled Optical Transceiver Module Based on a Single Holey CMOS IC

Journal of lightwave technology, 2011, Vol.29 (1-4), p.542-553

2011

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A Single-Chip CMOS-Based Parallel Optical Transceiver Capable of 240-Gb/s Bidirectional Data Rates

Journal of lightwave technology, 2009-04, Vol.27 (7), p.915-929

2009

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Electrical Performance of the Recessed Probe Launch Technique for Measurement of Embedded Multilayer Structures

IEEE transactions on instrumentation and measurement, 2012-12, Vol.61 (12), p.3198-3206

2012

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Accuracy of Physics-Based Via Models for Simulation of Dense Via Arrays

IEEE transactions on electromagnetic compatibility, 2012-10, Vol.54 (5), p.1125-1136

2012

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A 24-Channel, 300 Gb/s, 8.2 pJ/bit, Full-Duplex Fiber-Coupled Optical Transceiver Module Based on a Single "Holey" CMOS IC

Journal of lightwave technology, 2011-02, Vol.29 (4), p.542-553

2011

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Modeling On-Board Via Stubs and Traces in High-Speed Channels for Achieving Higher Data Bandwidth

IEEE transactions on components, packaging, and manufacturing technology (2011), 2014-02, Vol.4 (2), p.268-278

2014

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Using Via Stubs in Periodic Structures for Microwave Filter Design

IEEE transactions on components, packaging, and manufacturing technology (2011), 2014-07, Vol.4 (7), p.1212-1221

2014

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Application of the Short-Pulse Propagation Technique for Broadband Characterization of PCB and Other Interconnect Technologies

IEEE transactions on electromagnetic compatibility, 2010-05, Vol.52 (2), p.266-287

2010

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Signal integrity: Efficient, physics-based via modeling: Return path, impedance, and stub effect control

IEEE electromagnetic compatibility magazine, 2014-01, Vol.3 (1), p.76-84

2014

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Experimental validation of an 8 GHz EBG based common mode filter and impact of manufacturing uncertainties

2013 IEEE International Symposium on Electromagnetic Compatibility, 2013, p.27-32

2013

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High frequency measurement techniques for vias in printed circuit boards

IEEE electromagnetic compatibility magazine, 2014-01, Vol.3 (4), p.104-113

2014

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A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014, p.1-4

2014

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Model-to-hardware correlation of physics based via models with the parallel plate impedance included

2006 IEEE International Symposium on Electromagnetic Compatibility, 2006. EMC 2006, 2006, Vol.3, p.781-785

2006

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An Efficient Hybrid Finite-Element Analysis of Multiple Vias Sharing the Same Anti-Pad in an Arbitrarily Shaped Parallel-Plate Pair

IEEE transactions on microwave theory and techniques, 2015-03, Vol.63 (3), p.883-890

2015

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120-Gb/s VCSEL-based parallel-optical interconnect and custom 120-Gb/s testing station

Journal of lightwave technology, 2004-09, Vol.22 (9), p.2200-2212

2004

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Development of a Compact 28-GHz Software- Defined Phased Array for a City-Scale Wireless Research Testbed

2021 IEEE MTT-S International Microwave Symposium (IMS), 2021, p.803-806

2021

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A 1.4 pJ/bit, Power-Scalable 1612 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

IEEE journal of solid-state circuits, 2015-08, Vol.50 (8), p.1917-1931

2015

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15.6-Gb/s transmission over 1 km of next generation multimode fiber

IEEE photonics technology letters, 2002-05, Vol.14 (5), p.717-719

2002

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Spiral inductors and transmission lines in silicon technology using copper-damascene interconnects and low-loss substrates

IEEE transactions on microwave theory and techniques, 1997-10, Vol.45 (10), p.1961-1968

1997

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Development, Implementation, and Characterization of a 64-Element Dual-Polarized Phased-Array Antenna Module for 28-GHz High-Speed Data Communications

Physics-Based Via and Trace Models for Efficient Link Simulation on Multilayer Structures Up to 40 GHz

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

Energy-Aware Signal Integrity Analysis for High-Speed PCB Links

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

Efficient Prediction of Equalization Effort and Channel Performance for PCB-Based Data Links

A 24-Channel, 300 Gb/s, 8.2 pJ/bit, Full-Duplex Fiber-Coupled Optical Transceiver Module Based on a Single Holey CMOS IC

A Single-Chip CMOS-Based Parallel Optical Transceiver Capable of 240-Gb/s Bidirectional Data Rates

Electrical Performance of the Recessed Probe Launch Technique for Measurement of Embedded Multilayer Structures

Accuracy of Physics-Based Via Models for Simulation of Dense Via Arrays

A 24-Channel, 300 Gb/s, 8.2 pJ/bit, Full-Duplex Fiber-Coupled Optical Transceiver Module Based on a Single "Holey" CMOS IC

Modeling On-Board Via Stubs and Traces in High-Speed Channels for Achieving Higher Data Bandwidth

Using Via Stubs in Periodic Structures for Microwave Filter Design

Application of the Short-Pulse Propagation Technique for Broadband Characterization of PCB and Other Interconnect Technologies

Signal integrity: Efficient, physics-based via modeling: Return path, impedance, and stub effect control

Experimental validation of an 8 GHz EBG based common mode filter and impact of manufacturing uncertainties

High frequency measurement techniques for vias in printed circuit boards

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology

Model-to-hardware correlation of physics based via models with the parallel plate impedance included

An Efficient Hybrid Finite-Element Analysis of Multiple Vias Sharing the Same Anti-Pad in an Arbitrarily Shaped Parallel-Plate Pair

120-Gb/s VCSEL-based parallel-optical interconnect and custom 120-Gb/s testing station

Development of a Compact 28-GHz Software- Defined Phased Array for a City-Scale Wireless Research Testbed

A 1.4 pJ/bit, Power-Scalable 1612 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

15.6-Gb/s transmission over 1 km of next generation multimode fiber

Spiral inductors and transmission lines in silicon technology using copper-damascene interconnects and low-loss substrates

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