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A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.222-598

2007

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A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

IEEE journal of solid-state circuits, 2002-12, Vol.37 (12), p.1822-1830

2002

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A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361), 1999, p.339-341

1999

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A 622 Mb/s CMOS clock recovery PLL with time-interleaved phase detector array

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC, 1996, p.198-199

1996

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A 20-GHz phase-locked loop for 40Gb/s serializing transmitter in 0.13/spl mu/m CMOS

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005, 2005, p.144-147

2005

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A quad 3.125 Gbps transceiver cell with all-digital data recovery circuits

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005, 2005, p.384-387

2005

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A 5Gb/s 0.25/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Vol.2, p.206-474

2002

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A 5 Gb/s 0.25 /spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Vol.1, p.256-465 vol.1

2002

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A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO

A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method

A 622 Mb/s CMOS clock recovery PLL with time-interleaved phase detector array

A 20-GHz phase-locked loop for 40Gb/s serializing transmitter in 0.13/spl mu/m CMOS

A quad 3.125 Gbps transceiver cell with all-digital data recovery circuits

A 5Gb/s 0.25/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A 5 Gb/s 0.25 /spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

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