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Peripheral vision function training contents for people with low vision with Python tkinter

2022 13th International Conference on Information and Communication Technology Convergence (ICTC), 2022, p.739-741

2022

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25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.350-352

2021

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IEEE_Xplore

Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory

2009 Symposium on VLSI Technology, 2009, p.192-193

2009

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IEEE_Xplore

Method to Achieve the Morphotropic Phase Boundary in Hf x Zr 1−x O 2 by Electric Field Cycling for DRAM Cell Capacitor Applications

IEEE electron device letters, 2021-04, Vol.42 (4), p.517-520

2021

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Effects of Armature Height and Position on the Performance of Induction Coil Launcher

IEEE transactions on plasma science, 2017-10, Vol.45 (10), p.2696-2700

2017

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IEEE_Xplore

Fabrication and Testing of a 600-kJ Pulsed Power System

IEEE transactions on plasma science, 2013-10, Vol.41 (10), p.2671-2674

2013

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IEEE_Xplore

Ultralow- \textit Amorphous Boron Nitride Film for Copper Interconnect Capping Layer

IEEE transactions on electron devices, 2023-03, p.1-6

2023

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IEEE_Xplore

Nanosecond High-Voltage Pulse Generator Using a Spiral Blumlein PFL for Electromagnetic Interference Test

IEEE transactions on plasma science, 2014-10, Vol.42 (10), p.2909-2912

2014

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IEEE_Xplore

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.378-380

2019

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IEEE_Xplore

Design and Test of an Electric Field Sensor for the Measurement of High-Voltage Nanosecond Pulses

IEEE transactions on plasma science, 2013-10, Vol.41 (10), p.2946-2950

2013

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IEEE_Xplore

A 4.8-MJ Pulsed-Power System for Electromagnetic Launcher Experiment

IEEE transactions on plasma science, 2015-10, Vol.43 (10), p.3369-3373

2015

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IEEE_Xplore

A 1.05A/m Minimum Magnetic Field Strength Single-Chip Fully Integrated Biometric Smart Card SoC Achieving 1014.7ms Transaction Time with Anti-Spoofing Fingerprint Authentication

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.504-506

2022

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IEEE_Xplore

Electromagnetic Launch Experiments Using a 4.8-MJ Pulsed Power Supply

IEEE transactions on plasma science, 2015-05, Vol.43 (5), p.1358-1361

2015

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IEEE_Xplore

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.234-236

2024

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IEEE_Xplore

Adaptive Coding Unit early termination algorithm for HEVC

2012 IEEE International Conference on Consumer Electronics (ICCE), 2012, p.261-262

2012

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IEEE_Xplore

EMI Radiated Emission Prediction of Full Bridge Inverter

2023 International Symposium on Electromagnetic Compatibility – EMC Europe, 2023, p.1-5

2023

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IEEE_Xplore

A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.130-131

2022

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A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process

2022 IEEE Custom Integrated Circuits Conference (CICC), 2022, p.1-2

2022

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IEEE_Xplore

Energy-Band-Engineered Unified-RAM (URAM) Cell on Buried \hbox\hbox Substrate for Multifunctioning Flash Memory and 1T-DRAM

IEEE transactions on electron devices, 2009-04, Vol.56 (4), p.641-647

2009

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IEEE_Xplore

A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.148-149

2022

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25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.346-348

2021

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IEEE_Xplore

Microstructure and Electrical Properties of Amorphous \hbox\hbox\hbox Films Grown on Cu/Ti/ \hbox/Si Substrates Using RF Magnetron Sputtering

IEEE transactions on electron devices, 2011-05, Vol.58 (5), p.1462-1467

2011

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IEEE_Xplore

Energy-Band-Engineered Unified-RAM (URAM) Cell on Buried hbox Si 1 a y hbox C y Substrate for Multifunctioning Flash Memory and 1T-DRAM

IEEE transactions on electron devices, 2009-01, Vol.56 (4)

2009

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Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology

2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers, 2006, p.32-33

2006

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IEEE_Xplore

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Peripheral vision function training contents for people with low vision with Python tkinter

25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications

Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory

Method to Achieve the Morphotropic Phase Boundary in Hf x Zr 1−x O 2 by Electric Field Cycling for DRAM Cell Capacitor Applications

Effects of Armature Height and Position on the Performance of Induction Coil Launcher

Fabrication and Testing of a 600-kJ Pulsed Power System

Ultralow- \textit Amorphous Boron Nitride Film for Copper Interconnect Capping Layer

Nanosecond High-Voltage Pulse Generator Using a Spiral Blumlein PFL for Electromagnetic Interference Test

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

Energy-Band-Engineered Unified-RAM (URAM) Cell on Buried [Formula Omitted] Substrate for Multifunctioning Flash Memory and 1T-DRAM

Design and Test of an Electric Field Sensor for the Measurement of High-Voltage Nanosecond Pulses

A 4.8-MJ Pulsed-Power System for Electromagnetic Launcher Experiment

A 1.05A/m Minimum Magnetic Field Strength Single-Chip Fully Integrated Biometric Smart Card SoC Achieving 1014.7ms Transaction Time with Anti-Spoofing Fingerprint Authentication

Electromagnetic Launch Experiments Using a 4.8-MJ Pulsed Power Supply

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process

Adaptive Coding Unit early termination algorithm for HEVC

EMI Radiated Emission Prediction of Full Bridge Inverter

A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features

A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process

Energy-Band-Engineered Unified-RAM (URAM) Cell on Buried \hbox\hbox Substrate for Multifunctioning Flash Memory and 1T-DRAM

A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM

Microstructure and Electrical Properties of Amorphous \hbox\hbox\hbox Films Grown on Cu/Ti/ \hbox/Si Substrates Using RF Magnetron Sputtering

Energy-Band-Engineered Unified-RAM (URAM) Cell on Buried hbox Si 1 a y hbox C y Substrate for Multifunctioning Flash Memory and 1T-DRAM

Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology

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