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Near Volatile and Non-Volatile Memory Processing in 3D Systems

IEEE transactions on emerging topics in computing, 2022-07, Vol.10 (3), p.1657-1664

2022

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IEEE_Xplore

NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-07, Vol.31 (7), p.994-1007

2012

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IEEE_Xplore

HeteroOS - OS design for heterogeneous memory management in datacenter

2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017, p.521-534

2017

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In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands

IEEE transactions on very large scale integration (VLSI) systems, 2020-05, Vol.28 (5), p.1316-1320

2020

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IEEE_Xplore

RTSim: A Cycle-Accurate Simulator for Racetrack Memories

IEEE computer architecture letters, 2019-01, Vol.18 (1), p.43-46

2019

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IEEE_Xplore

Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory

IEEE transactions on very large scale integration (VLSI) systems, 2013-06, Vol.21 (6), p.1094-1102

2013

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IEEE_Xplore

An Effective Selection of Memory Technologies for TCAM to Improve the Search Operations: Demonstration of Memory Efficiency in SDN Recovery

Electronics (Basel), 2024-02, Vol.13 (4), p.707

2024

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Generalized Key-Value Memory to Flexibly Adjust Redundancy in Memory-Augmented Networks

IEEE transaction on neural networks and learning systems, 2023-12, Vol.34 (12), p.10993-10998

2023

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IEEE_Xplore

McDRAM: Low Latency and Energy-Efficient Matrix Computations in DRAM

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-11, Vol.37 (11), p.2613-2622

2018

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IEEE_Xplore

NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems

IEEE computer architecture letters, 2015-07, Vol.14 (2), p.140-143

2015

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IEEE_Xplore

Ramulator: A Fast and Extensible DRAM Simulator

IEEE computer architecture letters, 2016-01, Vol.15 (1), p.45-49

2016

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IEEE_Xplore

Dynamic Adaptive Replacement Policy in Shared Last-Level Cache of DRAM/PCM Hybrid Memory for Big Data Storage

IEEE transactions on industrial informatics, 2017-08, Vol.13 (4), p.1951-1960

2017

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IEEE_Xplore

Leveraging Write Heterogeneity of Phase Change Memory on Supporting Self-Balancing Binary Tree

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-06, Vol.41 (6), p.1757-1770

2022

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IEEE_Xplore

Fundamental Limits on the Precision of In-memory Architectures

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-9

2020

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IEEE_Xplore

Dynamic Power Reduction in TCAM Using Advanced Selective Pre-Charging of Match Lines

Electronics (Basel), 2023-09, Vol.12 (17), p.3691

2023

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Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems

2008 International Symposium on Computer Architecture, 2008, p.63-74

2008

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IEEE_Xplore

An Adaptive Memory-Side Encryption Method for Improving Security and Lifetime of PCM-Based Main Memory

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-06, Vol.41 (6), p.1744-1756

2022

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IEEE_Xplore

DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

IEEE access, 2021, Vol.9, p.134457-134502

2021

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SRAM Compilation and Placement Co-Optimization for Memory Subsystems

Electronics (Basel), 2023-03, Vol.12 (6), p.1353

Liu, Biwei

2023

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Boosting NVDIMM Performance With a Lightweight Caching Algorithm

IEEE transactions on very large scale integration (VLSI) systems, 2018-08, Vol.26 (8), p.1518-1530

2018

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IEEE_Xplore

Miss Penalty Aware Cache Replacement for Hybrid Memory Systems

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.4669-4682

2020

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Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory

Electronics (Basel), 2022-09, Vol.11 (17), p.2738

2022

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A Streaming Data Processing Architecture Based on Lookup Tables

Electronics (Basel), 2023-06, Vol.12 (12), p.2725

2023

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Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology

2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2017, p.273-287

2017

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IEEE_Xplore

Object-Level Memory Allocation and Migration in Hybrid Memory Systems

IEEE transactions on computers, 2020-09, Vol.69 (9), p.1401-1413

2020

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Near Volatile and Non-Volatile Memory Processing in 3D Systems

NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory

HeteroOS - OS design for heterogeneous memory management in datacenter

In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands

RTSim: A Cycle-Accurate Simulator for Racetrack Memories

Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory

An Effective Selection of Memory Technologies for TCAM to Improve the Search Operations: Demonstration of Memory Efficiency in SDN Recovery

Generalized Key-Value Memory to Flexibly Adjust Redundancy in Memory-Augmented Networks

McDRAM: Low Latency and Energy-Efficient Matrix Computations in DRAM

NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems

Ramulator: A Fast and Extensible DRAM Simulator

Dynamic Adaptive Replacement Policy in Shared Last-Level Cache of DRAM/PCM Hybrid Memory for Big Data Storage

Leveraging Write Heterogeneity of Phase Change Memory on Supporting Self-Balancing Binary Tree

Fundamental Limits on the Precision of In-memory Architectures

Dynamic Power Reduction in TCAM Using Advanced Selective Pre-Charging of Match Lines

Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems

An Adaptive Memory-Side Encryption Method for Improving Security and Lifetime of PCM-Based Main Memory

DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

SRAM Compilation and Placement Co-Optimization for Memory Subsystems

Boosting NVDIMM Performance With a Lightweight Caching Algorithm

Miss Penalty Aware Cache Replacement for Hybrid Memory Systems

Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory

A Streaming Data Processing Architecture Based on Lookup Tables

Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology

Object-Level Memory Allocation and Migration in Hybrid Memory Systems

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