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In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands

IEEE transactions on very large scale integration (VLSI) systems, 2020-05, Vol.28 (5), p.1316-1320

2020

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Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory

IEEE transactions on very large scale integration (VLSI) systems, 2013-06, Vol.21 (6), p.1094-1102

2013

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Multibit Content Addressable Memory Design and Optimization Based on 3-D nand-Compatible IGZO Flash

IEEE transactions on very large scale integration (VLSI) systems, 2024-08, Vol.32 (8), p.1380-1388

2024

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Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory

IEEE transactions on very large scale integration (VLSI) systems, 2020-12, Vol.28 (12), p.2636-2649

2020

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Resource-Efficient SRAM-Based Ternary Content Addressable Memory

IEEE transactions on very large scale integration (VLSI) systems, 2017-04, Vol.25 (4), p.1583-1587

2017

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Boosting NVDIMM Performance With a Lightweight Caching Algorithm

IEEE transactions on very large scale integration (VLSI) systems, 2018-08, Vol.26 (8), p.1518-1530

2018

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Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

IEEE transactions on very large scale integration (VLSI) systems, 2021-06, Vol.29 (6), p.1108-1121

2021

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ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators

IEEE transactions on very large scale integration (VLSI) systems, 2021-04, Vol.29 (4), p.702-715

2021

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Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines

IEEE transactions on very large scale integration (VLSI) systems, 2011-08, Vol.19 (8), p.1407-1417

2011

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Compute-in-Memory Technologies and Architectures for Deep Learning Workloads

IEEE transactions on very large scale integration (VLSI) systems, 2022-11, Vol.30 (11), p.1-16

2022

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Computing in Memory With Spin-Transfer Torque Magnetic RAM

IEEE transactions on very large scale integration (VLSI) systems, 2018-03, Vol.26 (3), p.470-483

2018

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High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications

IEEE transactions on very large scale integration (VLSI) systems, 2023-04, Vol.31 (4), p.522-531

2023

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DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates

IEEE transactions on very large scale integration (VLSI) systems, 2019-06, Vol.27 (6), p.1298-1307

2019

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PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks

IEEE transactions on very large scale integration (VLSI) systems, 2019-11, Vol.27 (11), p.2668-2679

2019

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A 2-D Calibration Scheme for Resistive Nonvolatile Memories

IEEE transactions on very large scale integration (VLSI) systems, 2020-06, Vol.28 (6), p.1371-1377

2020

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Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches

IEEE transactions on very large scale integration (VLSI) systems, 2018-10, Vol.26 (10), p.1881-1894

2018

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PFHA: A Novel Page Migration Algorithm for Hybrid Memory Embedded Systems

IEEE transactions on very large scale integration (VLSI) systems, 2021-10, Vol.29 (10), p.1685-1692

2021

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Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed

IEEE transactions on very large scale integration (VLSI) systems, 2010-01, Vol.18 (1), p.66-74

2010

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ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration

IEEE transactions on very large scale integration (VLSI) systems, 2018-12, Vol.26 (12), p.2781-2794

2018

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RA-Aware Fail Data Collection Architecture for Cost Reduction

IEEE transactions on very large scale integration (VLSI) systems, 2024-06, Vol.32 (6), p.1136-1149

2024

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An Efficient NVM-Based Architecture for Intermittent Computing Under Energy Constraints

IEEE transactions on very large scale integration (VLSI) systems, 2023-06, Vol.31 (6), p.725-737

2023

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A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store

IEEE transactions on very large scale integration (VLSI) systems, 2023-06, Vol.31 (6), p.776-788

2023

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ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

IEEE transactions on very large scale integration (VLSI) systems, 2020-04, Vol.28 (4), p.1084-1088

2020

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True Random Number Generation Using Latency Variations of FRAM

IEEE transactions on very large scale integration (VLSI) systems, 2021-01, Vol.29 (1), p.14-23

2021

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A 40-nm SONOS Digital CIM Using Simplified LUT Multiplier and Continuous Sample-Hold Sense Amplifier for AI Edge Inference

IEEE transactions on very large scale integration (VLSI) systems, 2023-12, Vol.31 (12), p.2044-2052

2023

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In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands

Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory

Multibit Content Addressable Memory Design and Optimization Based on 3-D nand-Compatible IGZO Flash

Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory

Resource-Efficient SRAM-Based Ternary Content Addressable Memory

Boosting NVDIMM Performance With a Lightweight Caching Algorithm

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators

Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines

Compute-in-Memory Technologies and Architectures for Deep Learning Workloads

Computing in Memory With Spin-Transfer Torque Magnetic RAM

High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications

DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates

PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks

A 2-D Calibration Scheme for Resistive Nonvolatile Memories

Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches

PFHA: A Novel Page Migration Algorithm for Hybrid Memory Embedded Systems

Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed

ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration

RA-Aware Fail Data Collection Architecture for Cost Reduction

An Efficient NVM-Based Architecture for Intermittent Computing Under Energy Constraints

A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store

ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

True Random Number Generation Using Latency Variations of FRAM

A 40-nm SONOS Digital CIM Using Simplified LUT Multiplier and Continuous Sample-Hold Sense Amplifier for AI Edge Inference

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