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2.4-GHz High-Efficiency Adaptive Power

IEEE transactions on very large scale integration (VLSI) systems, 2014-02, Vol.22 (2), p.434-438

2014

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Multi-Mode VCSEL Chip with High-Indium-Density InGaAs/AlGaAs Quantum-Well Pairs for QAM-OFDM in Multi-Mode Fiber

IEEE journal of quantum electronics, 2017-08, Vol.53 (4), p.1-8

2017

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A SAR-Assisted Continuous-Time Incremental ΣΔ ADC With First-Order Noise Coupling

2019 IEEE 13th International Conference on ASIC (ASICON), 2019, p.1-4

2019

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A 200-MS/s Phase-Detector-Based Comparator With 400- \mu\text} Noise

IEEE transactions on circuits and systems. II, Express briefs, 2016-09, Vol.63 (9), p.813-817

2016

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A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.514-632

2008

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A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010, p.300-301

2010

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A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, p.1328-1331

2014

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A Calibration-Free 9.3-ENOB 1-GS/s Pipelined ADC With PVT-Insensitive Nested Ring Amplifiers

IEEE transactions on circuits and systems. II, Express briefs, 2024-09, p.1-1

2024

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An 800-MS/s 8.2-ENOB TDC-assisted Pipelined-SAR ADC With Parallel Conversion

IEEE transactions on circuits and systems. II, Express briefs, 2024-08, p.1-1

2024

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An thermoelectric and RF multi-source energy harvesting system

2016 2nd International Conference on Intelligent Green Building and Smart Grid (IGBSG), 2016, p.1-5

2016

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A single-channel 10-b 400-MS/s 8.7-mW pipeline ADC in a 90-nm technology

2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2015, p.1-4

2015

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A Delay-Line-Based GFSK Demodulator for Low-IF Receivers

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.88-589

2007

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iTPlace: machine learning-based delay-aware transistor placement for standard cell synthesis

Proceedings of the 39th International Conference on Computer-Aided Design, 2020, p.1-8

2020

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A 5 GHz Fractional-[Formula Omitted] ADC-Based Digital Phase-Locked Loops With -243.8 dB FOM

IEEE transactions on circuits and systems. I, Regular papers, 2016-11, Vol.63 (11), p.1845

2016

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A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique

2014 Symposium on VLSI Circuits Digest of Technical Papers, 2014, p.1-2

2014

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A 10-Gb/s equalizer with digital adaptation

2017 International SoC Design Conference (ISOCC), 2017, p.38-39

2017

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A technique for in-band phase noise reduction in fractional-N frequency synthesizers

2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2016, p.273-276

2016

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A 12-bit 600-MS/s time-interleaved SAR ADC with background timing skew calibration

2016 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2016, p.1-3

2016

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25.6 A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.390-392

2020

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A 5.12-GHz fractional-N frequency synthesizer with an LC-VCO-based MDLL

2017 Symposium on VLSI Circuits, 2017, p.C132-C133

2017

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SSCS-Taipei Chapter Holds Integrated Circuit Design Workshop on Ultra-Low-Voltage Design in Advanced CMOS Technology [Conference Reports]

IEEE solid state circuits magazine, 2016, Vol.8 (2), p.120-121

2016

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An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter technique

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2017, p.53-56

2017

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An optimization technique for RF buffers with active inductors

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.3692-3695 Vol. 4

2005

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A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2014, p.289-292

2014

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A 84.7-DR wide BW incremental ADC using CT structure

VLSI Design, Automation and Test(VLSI-DAT), 2015, p.1-4

2015

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2.4-GHz High-Efficiency Adaptive Power

Multi-Mode VCSEL Chip with High-Indium-Density InGaAs/AlGaAs Quantum-Well Pairs for QAM-OFDM in Multi-Mode Fiber

A SAR-Assisted Continuous-Time Incremental ΣΔ ADC With First-Order Noise Coupling

A 200-MS/s Phase-Detector-Based Comparator With 400- \mu\text} Noise

A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation

A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique

A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator

A Calibration-Free 9.3-ENOB 1-GS/s Pipelined ADC With PVT-Insensitive Nested Ring Amplifiers

An 800-MS/s 8.2-ENOB TDC-assisted Pipelined-SAR ADC With Parallel Conversion

An thermoelectric and RF multi-source energy harvesting system

A single-channel 10-b 400-MS/s 8.7-mW pipeline ADC in a 90-nm technology

A Delay-Line-Based GFSK Demodulator for Low-IF Receivers

iTPlace: machine learning-based delay-aware transistor placement for standard cell synthesis

A 5 GHz Fractional-[Formula Omitted] ADC-Based Digital Phase-Locked Loops With -243.8 dB FOM

A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique

A 10-Gb/s equalizer with digital adaptation

A technique for in-band phase noise reduction in fractional-N frequency synthesizers

A 12-bit 600-MS/s time-interleaved SAR ADC with background timing skew calibration

25.6 A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique

A 5.12-GHz fractional-N frequency synthesizer with an LC-VCO-based MDLL

SSCS-Taipei Chapter Holds Integrated Circuit Design Workshop on Ultra-Low-Voltage Design in Advanced CMOS Technology [Conference Reports]

An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter technique

An optimization technique for RF buffers with active inductors

A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit

A 84.7-DR wide BW incremental ADC using CT structure

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