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A 0.078 pJ/SOP Unstructured Sparsity-Aware Spiking Attention/Convolution Processor with 3D Compute Array

2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, p.1-2

2024

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IEEE_Xplore

A 1.2 NS GaAs 4kb Read-Only-Memory Fabricated by 0.5 µm-Gate BP-Saint

1987 IEEE GaAs IC Symposium Technical Digest, 1987, p.189-192

1987

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IEEE_Xplore

A 1-Mb RRAM Macro With 9.8 ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation

IEEE transactions on circuits and systems. II, Express briefs, 2024-05, Vol.71 (5), p.2564-2568

2024

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IEEE_Xplore

1-Mbit 3D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs

IEEE journal of the Electron Devices Society, 2024-02, p.1-1

2024

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A 1-TFLOPS/W, 28-nm Deep Neural Network Accelerator Featuring Online Compression and Decompression and BF16 Digital In-Memory-Computing Hardware

2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, p.1-2

2024

Link zum Volltext
IEEE_Xplore

100 años del Centro Zamorano de Buenos Aires. El cuidado de la memoria colectiva: objetos e indumentaria

Cuadernos del Centro de Estudios en Diseño y Comunicación. Ensayos, 2024 (216), p.17-30

Calvo, Florencia

2024

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A 106TOPS/W SRAM Compute-in-Memory Macro in 28NM With Reconfigurable Bitwise Operation for AI

2024 Conference of Science and Technology for Integrated Circuits (CSTIC), 2024, p.1-3

2024

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10Gb/s Programmable Driver with Active Termination

Pereira, Nuno Alves

2017

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ProQuest

A 10T2C Capacitive SRAM-based Computing-In-Memory Macro with Array-Embedded DAC and Shift-and-Add Functions

2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, p.1-2

2024

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IEEE_Xplore

11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.210-212

2024

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IEEE_Xplore

11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.212-214

2024

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IEEE_Xplore

A 110NM BCD-ON-SOI Technology Offering Best-In-Class Nonvolatile Memory IP for Automotive Application

2024 Conference of Science and Technology for Integrated Circuits (CSTIC), 2024, p.1-3

2024

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A 118 GOPS/mm23D eDRAM TensorCore Architecture for Large-scale Matrix Multiplication

2023 IEEE 30th International Conference on High Performance Computing, Data, and Analytics (HiPC), 2023, p.61-65

2023

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IEEE_Xplore

12.3 A Scalable and Instantaneously Wideband 5GS/s RF Correlator Based on Charge Thresholding Achieving 8-bit ENOB and 152 TOPS/W Compute Efficiency

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.222-224

2024

Link zum Volltext
IEEE_Xplore

13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.236-237

2024

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IEEE_Xplore

13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.238-240

2024

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IEEE_Xplore

13.5 A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis Capacitive-Peaking Crosstalk-Cancellation Scheme for Memory Interfaces in 28nm CMOS

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.240-242

2024

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IEEE_Xplore

13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.242-244

2024

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IEEE_Xplore

13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.246-248

2024

Link zum Volltext
IEEE_Xplore

13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.248-250

2024

Link zum Volltext
IEEE_Xplore

15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.276-278

2024

Link zum Volltext
IEEE_Xplore

15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.278-280

2024

Link zum Volltext
IEEE_Xplore

15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.280-282

2024

Link zum Volltext
IEEE_Xplore

15.5 LISA: A 576×4 All-in-One Replica-Spins Continuous-Time Latch-Based Ising Computer Using Massively-Parallel Random-Number Generations and Replica Equalizations

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.284-286

2024

Link zum Volltext
IEEE_Xplore

15.7 A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249μm2 Bit-Cell, a 3.2GB/S Read Throughput, a 10KCycle Write Endurance and a 10-Year Retention at 105°C

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.288-290

2024

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IEEE_Xplore

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A 0.078 pJ/SOP Unstructured Sparsity-Aware Spiking Attention/Convolution Processor with 3D Compute Array

A 1.2 NS GaAs 4kb Read-Only-Memory Fabricated by 0.5 µm-Gate BP-Saint

A 1-Mb RRAM Macro With 9.8 ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation

1-Mbit 3D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs

A 1-TFLOPS/W, 28-nm Deep Neural Network Accelerator Featuring Online Compression and Decompression and BF16 Digital In-Memory-Computing Hardware

100 años del Centro Zamorano de Buenos Aires. El cuidado de la memoria colectiva: objetos e indumentaria

A 106TOPS/W SRAM Compute-in-Memory Macro in 28NM With Reconfigurable Bitwise Operation for AI

10Gb/s Programmable Driver with Active Termination

A 10T2C Capacitive SRAM-based Computing-In-Memory Macro with Array-Embedded DAC and Shift-and-Add Functions

11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint

11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge

A 110NM BCD-ON-SOI Technology Offering Best-In-Class Nonvolatile Memory IP for Automotive Application

A 118 GOPS/mm23D eDRAM TensorCore Architecture for Large-scale Matrix Multiplication

12.3 A Scalable and Instantaneously Wideband 5GS/s RF Correlator Based on Charge Thresholding Achieving 8-bit ENOB and 152 TOPS/W Compute Efficiency

13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate

13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization

13.5 A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis Capacitive-Peaking Crosstalk-Cancellation Scheme for Memory Interfaces in 28nm CMOS

13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration

13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction

13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency

15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch

15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia

15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture

15.5 LISA: A 576×4 All-in-One Replica-Spins Continuous-Time Latch-Based Ising Computer Using Massively-Parallel Random-Number Generations and Replica Equalizations

15.7 A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249μm2 Bit-Cell, a 3.2GB/S Read Throughput, a 10KCycle Write Endurance and a 10-Year Retention at 105°C

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