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Epidermal thymic stromal lymphopoietin predicts the development of atopic dermatitis during infancy

Journal of allergy and clinical immunology, 2016-04, Vol.137 (4), p.1282-1285.e4

2016

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A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface

IEEE journal of solid-state circuits, 2017-06, Vol.52 (6), p.1563-1575

2017

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Fast Output Voltage-Regulated PWM Buck Converter With an Adaptive Ramp Amplitude Control

IEEE transactions on circuits and systems. II, Express briefs, 2013-10, Vol.60 (10), p.712-716

2013

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A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

IEEE journal of solid-state circuits, 2012-04, Vol.47 (4), p.981-989

2012

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Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH

IEEE journal of solid-state circuits, 2013-04, Vol.48 (4), p.948-959

2013

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CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction

IEEE transactions on circuits and systems. II, Express briefs, 2009-01, Vol.56 (1), p.11-15

2009

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A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity

IEEE transactions on circuits and systems. II, Express briefs, 2011-10, Vol.58 (10), p.632-636

2011

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Conditional-capture flip-flop for statistical power reduction

IEEE journal of solid-state circuits, 2001-08, Vol.36 (8), p.1263-1271

2001

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A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

IEEE journal of solid-state circuits, 2011-01, Vol.46 (1), p.107-118

2011

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P‐200: N‐type Host Derived from Phenyl‐Triazine Moiety for Low Driving Voltage in Blue Phosphorescent Organic Light‐Emitting Diodes

SID International Symposium Digest of technical papers, 2024-06, Vol.55 (1), p.2147-2149

2024

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A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking

IEEE journal of solid-state circuits, 2012, Vol.47 (1), p.107-116

2012

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Adaptive Digital Background Gain Mismatch Calibration for Multi-lane High-speed Serial Links

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2015, 15(1), 61, pp.96-100

2015

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A line inversion-based stepwise data driving for low-power mobile TFT-LCDs

IEEE transactions on consumer electronics, 2010-05, Vol.56 (2), p.1002-1009

2010

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Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation

IEEE transactions on circuits and systems. II, Express briefs, 2009-08, Vol.56 (8), p.649-653

2009

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High-Speed Low-Power Boosted Level Converters for Dual Supply Systems

IEICE transactions on electronics, 2012, Vol.E95.C (11), p.1824-1826

2012

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Temperature‐Adaptive Back‐Bias Voltage Generator for an RCAT Pseudo SRAM

ETRI Journal, 2010, 32(3), , pp.406-413

2010

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A Novel Body Bias Selection Scheme for Leakage Minimization

IEICE transactions on electronics, 2011, Vol.E94-C (9), p.1490-1493

2011

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Low-Power High-Speed Data Serializer for Mobile TFT-LCD Driver ICs

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2010, Vol.E93-A (12), p.2621-2622

2010

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A 6 Gbps/pin Low‐Power Half‐Duplex Active Cross‐Coupled LVDS Transceiver with Switched Termination

ETRI Journal, 2008, 30(4), , pp.612-614

2008

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0.37mW/Gb/s low power SLVS transmitter for battery powered applications

2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012, p.1955-1958

2012

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High-Speed Low-Power Global On-Chip Interconnect Based on Delayed Symbol Transmission

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2012, 12(2), 46, pp.168-174

2012

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A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel

IEEE Custom Integrated Circuits Conference 2010, 2010, p.1-4

2010

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48 MHz clock generating system for USB 2.0 with enhanced bandgap reference

CAS 2011 Proceedings (2011 International Semiconductor Conference), 2011, Vol.2, p.409-412

2011

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A low-power two-line inversion method for driving LCD panels

2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012, p.1995-1998

2012

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An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs

IEICE transactions on electronics, 2011, Vol.E94-C (10), p.1690-1697

2011

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Epidermal thymic stromal lymphopoietin predicts the development of atopic dermatitis during infancy

A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface

Fast Output Voltage-Regulated PWM Buck Converter With an Adaptive Ramp Amplitude Control

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH

CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction

A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity

Conditional-capture flip-flop for statistical power reduction

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

P‐200: N‐type Host Derived from Phenyl‐Triazine Moiety for Low Driving Voltage in Blue Phosphorescent Organic Light‐Emitting Diodes

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking

Adaptive Digital Background Gain Mismatch Calibration for Multi-lane High-speed Serial Links

A line inversion-based stepwise data driving for low-power mobile TFT-LCDs

Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation

High-Speed Low-Power Boosted Level Converters for Dual Supply Systems

Temperature‐Adaptive Back‐Bias Voltage Generator for an RCAT Pseudo SRAM

A Novel Body Bias Selection Scheme for Leakage Minimization

Low-Power High-Speed Data Serializer for Mobile TFT-LCD Driver ICs

A 6 Gbps/pin Low‐Power Half‐Duplex Active Cross‐Coupled LVDS Transceiver with Switched Termination

0.37mW/Gb/s low power SLVS transmitter for battery powered applications

High-Speed Low-Power Global On-Chip Interconnect Based on Delayed Symbol Transmission

A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel

48 MHz clock generating system for USB 2.0 with enhanced bandgap reference

A low-power two-line inversion method for driving LCD panels

An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs

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