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A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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1-Lipschitz Layers Compared: Memory, Speed, and Certifiable Robustness

2024 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), 2024, p.24574-24583

2024

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A 101mW, 280fps Scene Graph Generation Processor for Visual Context Understanding on Mobile Devices

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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108: Memory, Libido, and Obscenity between Paraguay and Brazil

Journal of Latin American cultural studies : travesía, 2024-04, Vol.33 (2), p.219-239

2024

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An 11 Gb/s 0.376 pJ/Bit Capacitor-Less Dicode Transceiver With Pattern-Dependent Equalizations TIA Termination for Parallel DRAM Interfaces

IEEE access, 2024, Vol.12, p.145934-145943

2024

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A 14 nm MRAM-Based Multi-bit Analog In-Memory Computing With Process-Variation Calibration for 72 Macros-Based Accelerator

IEEE solid-state circuits letters, 2024, Vol.7, p.295-298

2024

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14nm FinFET Node Embedded MRAM Technology for Automotive Non-Volatile RAM Applications with Endurance Over 1E12-Cycles

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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IL-2 delivery to CD8+ T cells during infection requires MRTF/SRF-dependent gene expression and cytoskeletal dynamics

Nature communications, 2024-09, Vol.15 (1), p.7956-20, Article 7956

2024

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20 години от приемането на Конвенцията на ЮНЕСКО за опазване на нематериалното културно наследство от 2003 г

Bŭlgarski folklor, 2023, Vol.XLIX (2), p.119-124

Curtis, Tim

2023

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A 2048×60m4 SRAM Design in Intel 4 With Around-the-Array Power Delivery Scheme Using PowerVia

IEEE solid-state circuits letters, 2024, Vol.7, p.243-246

2024

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A 20Gb/s/pin Single-Ended PAM-4 Transceiver with Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing for Low-Power Memory Interfaces

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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A 22-nm 264-GOPS/mm ^ 6T SRAM and Proportional Current Compute Cell-Based Computing-in-Memory Macro for CNNs

IEEE transactions on very large scale integration (VLSI) systems, 2024-09, p.1-5

2024

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2248 Clinical relevance of Donanemab treatment

Age and ageing, 2024-08, Vol.53 (Supplement_3)

2024

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A 22nm 10.03-237.99 TOPS/W Time-Digital-Hybrid SRAM Compute-in-Memory AI Accelerator for GNN Edge Device Applications

IEEE Transactions on Circuits and Systems for Artificial Intelligence, 2024-08, p.1-11

2024

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A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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25 finalists for PACE Awards chosen

Automotive News, 2024-08, Vol.98 (7156), p.34

Irwin, John

2024

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A 278-514M Event/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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A 28nm 4170-TFLOPS/W/b and 195-TFLOPS/mm2/b Multiply-Free Fully-Digital Floating-Point Compute-In-Memory Macro with Mitchell's Approximation

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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A 28nm Approximate / Binary 6T CAM for Sequence Alignment

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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A 3×12-Gb/s 1.26-pJ/b Single-Ended PAM-3 Transmitter With Crosstalk Cancellation Technique in 28-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2024-08, p.1-1

2024

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A 3.3GHz 1024X640 Multi-Bank Single-Port SRAM with Frequency Enhancing Techniques and 0.55V-1.35V Wide Voltage Range Operation in 3nm FinFET for HPC Applications

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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A 3.96- \mu m, 124-dB Dynamic-Range, Digital-Pixel Sensor With Triple-and Single-Quantization Operations for Monochrome and Near-Infrared Dual-Channel Global Shutter Operation

IEEE journal of solid-state circuits, 2024-10, p.1-11

2024

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A 3-D Pseudospectral Time-Domain Simulator for Large-Scale Electromagnetic Scattering and Radar Sounding Applications

IGARSS 2024 - 2024 IEEE International Geoscience and Remote Sensing Symposium, 2024, p.10570-10574

2024

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3 x 16 Gb/s Compact Single-Ended PAM4 Transmitters With Inverter-Based Crosstalk Compensation for Memory Interfaces

IEEE transactions on circuits and systems. II, Express briefs, 2024-08, p.1-1

2024

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3D-BBS: Global Localization for 3D Point Cloud Scan Matching Using Branch-and-Bound Algorithm

2024 IEEE International Conference on Robotics and Automation (ICRA), 2024, p.1796-1802

2024

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A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4

1-Lipschitz Layers Compared: Memory, Speed, and Certifiable Robustness

A 101mW, 280fps Scene Graph Generation Processor for Visual Context Understanding on Mobile Devices

108: Memory, Libido, and Obscenity between Paraguay and Brazil

An 11 Gb/s 0.376 pJ/Bit Capacitor-Less Dicode Transceiver With Pattern-Dependent Equalizations TIA Termination for Parallel DRAM Interfaces

A 14 nm MRAM-Based Multi-bit Analog In-Memory Computing With Process-Variation Calibration for 72 Macros-Based Accelerator

14nm FinFET Node Embedded MRAM Technology for Automotive Non-Volatile RAM Applications with Endurance Over 1E12-Cycles

IL-2 delivery to CD8+ T cells during infection requires MRTF/SRF-dependent gene expression and cytoskeletal dynamics

20 години от приемането на Конвенцията на ЮНЕСКО за опазване на нематериалното културно наследство от 2003 г

A 2048×60m4 SRAM Design in Intel 4 With Around-the-Array Power Delivery Scheme Using PowerVia

A 20Gb/s/pin Single-Ended PAM-4 Transceiver with Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing for Low-Power Memory Interfaces

A 22-nm 264-GOPS/mm ^ 6T SRAM and Proportional Current Compute Cell-Based Computing-in-Memory Macro for CNNs

2248 Clinical relevance of Donanemab treatment

A 22nm 10.03-237.99 TOPS/W Time-Digital-Hybrid SRAM Compute-in-Memory AI Accelerator for GNN Edge Device Applications

A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro

25 finalists for PACE Awards chosen

A 278-514M Event/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera

A 28nm 4170-TFLOPS/W/b and 195-TFLOPS/mm2/b Multiply-Free Fully-Digital Floating-Point Compute-In-Memory Macro with Mitchell's Approximation

A 28nm Approximate / Binary 6T CAM for Sequence Alignment

A 3×12-Gb/s 1.26-pJ/b Single-Ended PAM-3 Transmitter With Crosstalk Cancellation Technique in 28-nm CMOS

A 3.3GHz 1024X640 Multi-Bank Single-Port SRAM with Frequency Enhancing Techniques and 0.55V-1.35V Wide Voltage Range Operation in 3nm FinFET for HPC Applications

A 3.96- \mu m, 124-dB Dynamic-Range, Digital-Pixel Sensor With Triple-and Single-Quantization Operations for Monochrome and Near-Infrared Dual-Channel Global Shutter Operation

A 3-D Pseudospectral Time-Domain Simulator for Large-Scale Electromagnetic Scattering and Radar Sounding Applications

3 x 16 Gb/s Compact Single-Ended PAM4 Transmitters With Inverter-Based Crosstalk Compensation for Memory Interfaces

3D-BBS: Global Localization for 3D Point Cloud Scan Matching Using Branch-and-Bound Algorithm

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