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Design Insights of Nanosheet FET and CMOS Circuit Applications at 5-nm Technology Node

IEEE transactions on electron devices, 2022-08, Vol.69 (8), p.4115-4122

2022

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Design insights into RF/analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

International journal of RF and microwave computer-aided engineering, 2021-12, Vol.31 (12), p.n/a

2021

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Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes

International journal of electronics and communications, 2022-02, Vol.145, p.154069, Article 154069

2022

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Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length

International journal of electronics and communications, 2021-07, Vol.137, p.153803, Article 153803

2021

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p-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

ECS journal of solid state science and technology, 2021-12, Vol.10 (12), p.123001

2021

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Interface traps in the sub-3 nm technology node: A comprehensive analysis and benchmarking of negative capacitance FinFET and nanosheet FETs - A reliability perspective from device to circuit level

Microelectronics and reliability, 2024-09, Vol.160, p.115479, Article 115479

2024

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Beyond Moore's law – A critical review of advancements in negative capacitance field effect transistors: A revolution in next-generation electronics

Materials science in semiconductor processing, 2024-04, Vol.173, p.108116, Article 108116

2024

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Performance analysis of geometric variations in circular double gate MOSFETs at sub-7nm technology nodes

Microelectronics, 2023-12, Vol.142, p.105986, Article 105986

2023

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NDR free negative capacitance CGAAFET at 2nm technology node for low power and high-speed applications

Microelectronics, 2023-12, Vol.142, p.106018, Article 106018

2023

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Design Space Optimization for Eradication of NDR Effect in Dielectric/Ferroelectric Stacked Negative Capacitance Multi-Gate FETs at Sub-3nm Technology for Digital/Analog/RF Applications

IEEE transactions on dielectrics and electrical insulation, 2024-07, p.1-1

2024

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A novel step architecture based negative capacitance (SNC) FET: Design and circuit level analysis

Microelectronics, 2024-04, Vol.146, p.106139, Article 106139

2024

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Pushing the Boundaries: Design and Simulation Approach of Negative Capacitance Nanosheet FETs with Ferroelectric and Dielectric Spacers at the Sub‑3 nm Technology Node for Analog/RF/Mixed Signal Applications

ACS applied electronic materials, 2024-05, Vol.6 (5), p.3206-3215

2024

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Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

ECS journal of solid state science and technology, 2023-09, Vol.12 (9), p.93007

2023

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Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications

ECS journal of solid state science and technology, 2021-01, Vol.10 (1), p.13008

2021

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A Proposal for Optimization of Spacer Engineering at Sub-5-nm Technology Node for JL-TreeFET: A Device to Circuit Level Implementation

IEEE transactions on electron devices, 2024-01, Vol.71 (1), p.453-460

2024

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A novel bottom-spacer ground-plane (BSGP) FinFET for improved logic and analog/RF performance

International journal of electronics and communications, 2020-12, Vol.127, p.153459, Article 153459

2020

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Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes

Microelectronics, 2021-10, Vol.116, p.105214, Article 105214

2021

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Design and Performance Optimization of Junctionless Bottom Spacer FinFET for Digital/Analog/RF Applications at Sub-5nm Technology Node

ECS journal of solid state science and technology, 2023-01, Vol.12 (1), p.13004

2023

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A novel design of coplanar 8-bit ripple carry adder using field-coupled quantum-dot cellular automata nanotechnology

European physical journal plus, 2023-08, Vol.138 (8), p.731, Article 731

2023

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A two-dimensional (2D) analytical surface potential and subthreshold current model for the underlap dual-material double-gate (DMDG) FinFET

Journal of computational electronics, 2016-12, Vol.15 (4), p.1316-1325

2016

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Performance Investigation of FinFET Structures: Unleashing Multi-Gate Control through Design and Simulation at the 7 nm Technology Node for Next-Generation Electronic Devices

ECS journal of solid state science and technology, 2023-11, Vol.12 (11), p.113012

2023

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Dielectric Material and Thermal Optimization in Sidewall Spacer Design for Junctionless Nanosheet FETs at Sub- 5 nm Technology Node: An Insight into Device and Circuit Performance

ECS journal of solid state science and technology, 2024-10, Vol.13 (10), p.103007

2024

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Design Considerations into Circuit Applications for Structurally Optimised FinFET

ECS journal of solid state science and technology, 2023-12, Vol.12 (12), p.123007

2023

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Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective

ECS journal of solid state science and technology, 2024-01, Vol.13 (1), p.13002

2024

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A two-dimensional (2D) analytical surface potential and subthreshold current model for underlap dual-material double-gate (DMDG) FinFET

Journal of computational electronics, 2016-08

2016

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Design Insights of Nanosheet FET and CMOS Circuit Applications at 5-nm Technology Node

Design insights into RF/analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes

Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length

p-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

Interface traps in the sub-3 nm technology node: A comprehensive analysis and benchmarking of negative capacitance FinFET and nanosheet FETs - A reliability perspective from device to circuit level

Beyond Moore's law – A critical review of advancements in negative capacitance field effect transistors: A revolution in next-generation electronics

Performance analysis of geometric variations in circular double gate MOSFETs at sub-7nm technology nodes

NDR free negative capacitance CGAAFET at 2nm technology node for low power and high-speed applications

Design Space Optimization for Eradication of NDR Effect in Dielectric/Ferroelectric Stacked Negative Capacitance Multi-Gate FETs at Sub-3nm Technology for Digital/Analog/RF Applications

A novel step architecture based negative capacitance (SNC) FET: Design and circuit level analysis

Pushing the Boundaries: Design and Simulation Approach of Negative Capacitance Nanosheet FETs with Ferroelectric and Dielectric Spacers at the Sub‑3 nm Technology Node for Analog/RF/Mixed Signal Applications

Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications

A Proposal for Optimization of Spacer Engineering at Sub-5-nm Technology Node for JL-TreeFET: A Device to Circuit Level Implementation

A novel bottom-spacer ground-plane (BSGP) FinFET for improved logic and analog/RF performance

Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes

Design and Performance Optimization of Junctionless Bottom Spacer FinFET for Digital/Analog/RF Applications at Sub-5nm Technology Node

A novel design of coplanar 8-bit ripple carry adder using field-coupled quantum-dot cellular automata nanotechnology

A two-dimensional (2D) analytical surface potential and subthreshold current model for the underlap dual-material double-gate (DMDG) FinFET

Performance Investigation of FinFET Structures: Unleashing Multi-Gate Control through Design and Simulation at the 7 nm Technology Node for Next-Generation Electronic Devices

Dielectric Material and Thermal Optimization in Sidewall Spacer Design for Junctionless Nanosheet FETs at Sub- 5 nm Technology Node: An Insight into Device and Circuit Performance

Design Considerations into Circuit Applications for Structurally Optimised FinFET

Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective

A two-dimensional (2D) analytical surface potential and subthreshold current model for underlap dual-material double-gate (DMDG) FinFET

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