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European power grid reliability indicators, what do they really tell?

Electric power systems research, 2012-09, Vol.90, p.79-84

2012

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Critical State-Based Filtering System for Securing SCADA Network Protocols

IEEE transactions on industrial electronics (1982), 2012-10, Vol.59 (10), p.3943-3950

2012

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Uncertainty Propagation in Fault Tree Analyses Using Lognormal Distributions

IEEE transactions on reliability, 1987-04, Vol.R-36 (1), p.145-149

Masera, Marcelo

1987

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A Review of Available Software for the Creation of Testbeds for Internet Security Research

2009 First International Conference on Advances in System Simulation, 2009, p.79-87

2009

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Methodology for Experimental ICT Industrial and Critical Infrastructure Security Tests

2009 International Conference on Availability, Reliability and Security, 2009, p.400-405

2009

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A Secure and Survivable Architecture for SCADA Systems

2009 Second International Conference on Dependability, 2009, p.34-39

2009

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VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture

IEEE transactions on circuits and systems. I, Regular papers, 2013-06, Vol.60 (6), p.1441-1454

2013

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High Speed Architectures for Finding the First two Maximum/Minimum Values

IEEE transactions on very large scale integration (VLSI) systems, 2012-12, Vol.20 (12), p.2342-2346

2012

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State Metric Compression Techniques for Turbo Decoder Architectures

IEEE transactions on circuits and systems. I, Regular papers, 2011-05, Vol.58 (5), p.1119-1128

2011

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Multiplierless, Folded 9/7- 5/3 Wavelet VLSI Architecture

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2007-09, Vol.54 (9), p.770-774

2007

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An LDPC decoder architecture for wireless sensor network applications

Sensors (Basel, Switzerland), 2012-02, Vol.12 (2), p.1529-1543

2012

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Computation reduction for turbo decoding through window skipping

Electronics letters, 2016-02, Vol.52 (3), p.202-204

2016

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Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2006-11, Vol.53 (11), p.1289-1293

2006

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A Flexible UMTS-WiMax Turbo Decoder Architecture

IEEE transactions on circuits and systems. II, Express briefs, 2008-04, Vol.55 (4), p.369-373

2008

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Look-ahead sphere decoding: algorithm and VLSI architecture

IET communications, 2011-06, Vol.5 (9), p.1275-1285

2011

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Power Control for Crossbar-Based Input-Queued Switches

IEEE transactions on computers, 2013-01, Vol.62 (1), p.74-82

2013

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On Practical Implementation and Generalizations of \max^ Operator for Turbo and LDPC Decoders

IEEE transactions on instrumentation and measurement, 2012-04, Vol.61 (4), p.888-895

2012

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Efficient Implementation Techniques for Maximum Likelihood-Based Error Correction for JPEG2000

IEEE transactions on circuits and systems for video technology, 2009-04, Vol.19 (4), p.591-596

2009

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On chip interconnects for multiprocessor turbo decoding architectures

Microprocessors and microsystems, 2011-03, Vol.35 (2), p.167-181

2011

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VLSI architectures for turbo codes

IEEE transactions on very large scale integration (VLSI) systems, 1999-09, Vol.7 (3), p.369-379

1999

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Mumford and Shah functional: VLSI analysis and implementation

IEEE transactions on pattern analysis and machine intelligence, 2006-03, Vol.28 (3), p.487-494

2006

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An application specific instruction set processor based implementation for signal detection in multiple antenna systems

Microprocessors and microsystems, 2012-05, Vol.36 (3), p.245-256

2012

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Non-recursive max∗ operator with reduced implementation complexity for turbo decoding

IET communications, 2012-05, Vol.6 (7), p.702

2012

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Scalable low-complexity B-spline discrete wavelet transform architecture

IET circuits, devices & systems, 2010-03, Vol.4 (2), p.159-167

2010

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Architectural strategies for low-power VLSI turbo decoders

IEEE transactions on very large scale integration (VLSI) systems, 2002-06, Vol.10 (3), p.279-285

2002

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European power grid reliability indicators, what do they really tell?

Critical State-Based Filtering System for Securing SCADA Network Protocols

Uncertainty Propagation in Fault Tree Analyses Using Lognormal Distributions

A Review of Available Software for the Creation of Testbeds for Internet Security Research

Methodology for Experimental ICT Industrial and Critical Infrastructure Security Tests

A Secure and Survivable Architecture for SCADA Systems

VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture

High Speed Architectures for Finding the First two Maximum/Minimum Values

State Metric Compression Techniques for Turbo Decoder Architectures

Multiplierless, Folded 9/7- 5/3 Wavelet VLSI Architecture

An LDPC decoder architecture for wireless sensor network applications

Computation reduction for turbo decoding through window skipping

Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation

A Flexible UMTS-WiMax Turbo Decoder Architecture

Look-ahead sphere decoding: algorithm and VLSI architecture

Power Control for Crossbar-Based Input-Queued Switches

On Practical Implementation and Generalizations of \max^ Operator for Turbo and LDPC Decoders

Efficient Implementation Techniques for Maximum Likelihood-Based Error Correction for JPEG2000

On chip interconnects for multiprocessor turbo decoding architectures

VLSI architectures for turbo codes

Mumford and Shah functional: VLSI analysis and implementation

An application specific instruction set processor based implementation for signal detection in multiple antenna systems

Non-recursive max∗ operator with reduced implementation complexity for turbo decoding

Scalable low-complexity B-spline discrete wavelet transform architecture

Architectural strategies for low-power VLSI turbo decoders

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