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An Ultralow Power Time-Domain Temperature Sensor With Time-Domain Delta-Sigma TDC

IEEE transactions on circuits and systems. II, Express briefs, 2017-10, Vol.64 (10), p.1117-1121

2017

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11 b 200 MS/s 28‐nm CMOS 2b/cycle successive‐approximation register analogue‐to‐digital converter using offset‐mismatch calibrated comparators

Electronics letters, 2023-08, Vol.59 (16), p.n/a

2023

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High Frame-Rate VGA CMOS Image Sensor Using Non-Memory Capacitor Two-Step Single-Slope ADCs

IEEE transactions on circuits and systems. I, Regular papers, 2015-09, Vol.62 (9), p.2147-2155

2015

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A 13.5-mW 10-Gb/s 4-PAM Serial Link Transmitter in 0.13- \mu\hbox CMOS Technology

IEEE transactions on circuits and systems. II, Express briefs, 2014-09, Vol.61 (9), p.646-650

2014

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A 4-MHz Digitally Controlled Voltage-Mode Buck Converter With Embedded Transient Improvement Using Delay Line Control Techniques

IEEE transactions on circuits and systems. I, Regular papers, 2020-11, Vol.67 (11), p.4029-4040

2020

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A 30-MHz Voltage-Mode Buck Converter Using Delay-Line-Based PWM Control

IEEE transactions on circuits and systems. II, Express briefs, 2018-11, Vol.65 (11), p.1659-1663

2018

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Multi-Stage Reconfigurable RF-DC Converter With Deep- n -Well Biasing Using Body-Isolated MOSFET in 180-nm BCDMOS Process

IEEE transactions on circuits and systems. II, Express briefs, 2023-10, Vol.70 (10), p.3817-3821

2023

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A 6.5-12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS

IEEE journal of solid-state circuits, 2020-10, Vol.55 (10), p.2831-2841

2020

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Multi-Stage Reconfigurable RF-DC Converter with deep-n-well biasing using Body Isolated MOSFET in 180nm BCDMOS Process

IEEE transactions on circuits and systems. II, Express briefs, 2023-06, p.1-1

2023

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A 24.1 TOPS/W mixed-signal BNN processor in 28-nm CMOS

International journal of electronics, 2024-08, Vol.111 (8), p.1288-1300

2024

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A Phase Noise Optimized 4 GHz Differential Colpitts VCO

IEICE transactions on electronics, 2010, Vol.E93-C (3), p.420-422

2010

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Precise Individual Illumination Control of Matrix LED With Bypass Gate Driver and 8-Bit PWM

IEEE transactions on circuits and systems. II, Express briefs, 2024-08, p.1-1

2024

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1.5-9.7-Gb/s Complete 4-PAM Serial Link Transceiver with a Wide Frequency Range CDR

IEICE transactions on electronics, 2013, Vol.E96.C (8), p.1048-1053

2013

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A Low-Power Switching Method with a Bootstrapping Circuit for High-Speed Transmitters

IEICE transactions on electronics, 2012, Vol.E95.C (5), p.921-923

2012

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A 0.18.MU.m CMOS 12Gb/s 10-PAM Serial Link Transmitter

IEICE transactions on electronics, 2011, Vol.E94-C (11), p.1787-1793

2011

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A Sub-Harmonic RF Transmitter Architecture with Simultaneous Power Combination and LO Leakage Cancellation

IEICE transactions on electronics, 2011, Vol.E94-C (5), p.858-861

2011

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An Autofocus Sensor With Global Shutter Using Offset-Free Frame Memory

IEEE transactions on circuits and systems. II, Express briefs, 2010-11, Vol.57 (11), p.878-882

2010

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A 0.18-$\mu$m CMOS 10-Gb/s Dual-Mode 10-PAM Serial Link Transceiver

IEEE transactions on circuits and systems. I, Regular papers, 2013-02, Vol.60 (2), p.457-468

2013

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All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector

IEICE Electronics Express, 2020, Vol.17 (6), p.20200024-20200024

2020

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Quenching bias circuit with current mirror for single photon detection

IEICE Electronics Express, 2019, Vol.16 (23), p.20190657-20190657

2019

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75 Å GaN channel modulation doped field effect transistors

Applied physics letters, 1996-05, Vol.68 (20), p.2849-2851

1996

Volltextzugriff (PDF)

Two CMOS time to digital converters using successive approximation register logic

IEICE Electronics Express, 2018, Vol.15 (22), p.20180840-20180840

2018

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A low-complexity fast-locking digital PLL with multi-output bang-bang phase detector

2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2016, p.418-420

2016

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A 0.18-/spl mu/m CMOS 10-Gb/s Dual-Mode 10-PAM Serial Link Transceiver

IEEE transactions on circuits and systems. I, Regular papers, 2013-02, Vol.60 (2), p.457-468

2013

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Editorial

Journal of semiconductor technology and science, 2015, Vol.15 (4), p.518-518

2015

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An Ultralow Power Time-Domain Temperature Sensor With Time-Domain Delta-Sigma TDC

11 b 200 MS/s 28‐nm CMOS 2b/cycle successive‐approximation register analogue‐to‐digital converter using offset‐mismatch calibrated comparators

High Frame-Rate VGA CMOS Image Sensor Using Non-Memory Capacitor Two-Step Single-Slope ADCs

A 13.5-mW 10-Gb/s 4-PAM Serial Link Transmitter in 0.13- \mu\hbox CMOS Technology

A 4-MHz Digitally Controlled Voltage-Mode Buck Converter With Embedded Transient Improvement Using Delay Line Control Techniques

A 30-MHz Voltage-Mode Buck Converter Using Delay-Line-Based PWM Control

Multi-Stage Reconfigurable RF-DC Converter With Deep- n -Well Biasing Using Body-Isolated MOSFET in 180-nm BCDMOS Process

A 6.5-12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS

Multi-Stage Reconfigurable RF-DC Converter with deep-n-well biasing using Body Isolated MOSFET in 180nm BCDMOS Process

A 24.1 TOPS/W mixed-signal BNN processor in 28-nm CMOS

A Phase Noise Optimized 4 GHz Differential Colpitts VCO

Precise Individual Illumination Control of Matrix LED With Bypass Gate Driver and 8-Bit PWM

1.5-9.7-Gb/s Complete 4-PAM Serial Link Transceiver with a Wide Frequency Range CDR

A Low-Power Switching Method with a Bootstrapping Circuit for High-Speed Transmitters

A 0.18.MU.m CMOS 12Gb/s 10-PAM Serial Link Transmitter

A Sub-Harmonic RF Transmitter Architecture with Simultaneous Power Combination and LO Leakage Cancellation

An Autofocus Sensor With Global Shutter Using Offset-Free Frame Memory

A 0.18-$\mu$m CMOS 10-Gb/s Dual-Mode 10-PAM Serial Link Transceiver

All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector

Quenching bias circuit with current mirror for single photon detection

75 Å GaN channel modulation doped field effect transistors

Two CMOS time to digital converters using successive approximation register logic

A low-complexity fast-locking digital PLL with multi-output bang-bang phase detector

A 0.18-/spl mu/m CMOS 10-Gb/s Dual-Mode 10-PAM Serial Link Transceiver

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