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Gate-based high fidelity spin readout in a CMOS device

Nature nanotechnology, 2019-08, Vol.14 (8), p.737-741

2019

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Analysis of the Electrical Parameters of SOI Junctionless Nanowire Transistors at High Temperatures

IEEE journal of the Electron Devices Society, 2021, Vol.9, p.492-499

2021

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High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

IEEE journal of the Electron Devices Society, 2023-01, Vol.11, p.1-1

2023

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Process Variability-Technological Challenge and Design Issue for Nanoscale Devices

Micromachines (Basel), 2019-01, Vol.10 (1), p.6

2019

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Effects of channel width variation on electrical characteristics of tri-gate Junctionless transistors

Solid-state electronics, 2013-03, Vol.81, p.58-62

2013

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Development of a CMOS Route for Electron Pumps to Be Used in Quantum Metrology

Technologies (Basel), 2016-03, Vol.4 (1), p.10

2016

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Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures

IEEE journal of the Electron Devices Society, 2024-06, p.1-1

2024

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Bias dependent physics-based model of low-frequency noise for nanowire type gate-all-around MOSFETs

Solid-state electronics, 2022-03, Vol.189, p.108223, Article 108223

2022

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Impact of (Quasi-)Ballistic Transport on Operation of Complementary Metal–Oxide–Semiconductor Inverters Based on Fully-Depleted Silicon-on-Insulator and Nanowire Devices

Japanese Journal of Applied Physics, 2011-01, Vol.50 (1R), p.14103

2011

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Compact Analytical Model for Trap-Related Low Frequency Noise in Junctionless Transistors

ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC), 2019, p.194-197

2019

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Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC), 2021, p.223-226

2021

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Method for Extracting Doping Concentration and Flat-Band Voltage in Junctionless Multigate MOSFETs Using 2-D Electrostatic Effects

IEEE electron device letters, 2013-08, Vol.34 (8), p.957-959

2013

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SET Sensitivity of Trigate Silicon Nanowire Field-Effect Transistors

IEEE transactions on nuclear science, 2019-01, Vol.66 (1), p.352-358

2019

Volltextzugriff (PDF)

Gate-based high fidelity spin readout in a CMOS device

Nature nanotechnology, 2019-08, Vol.14 (8), p.737-741

2019

Volltextzugriff (PDF)

Readout and control of the spin-orbit states of two coupled acceptor atoms in a silicon transistor

Science advances, 2018-12, Vol.4 (12), p.eaat9199-eaat9199

2018

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Evaluation and implementation of High-Dimensionnal Computing for gesture recognition using sEMG signals

2024 International Conference on Control, Automation and Diagnosis (ICCAD), 2024, p.1-6

2024

Volltextzugriff (PDF)

Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K

Solid-state electronics, 2017-02, Vol.128, p.60-66

2017

Volltextzugriff (PDF)

A Simple Method for Estimation of Silicon Film Thickness in Tri-Gate Junctionless Transistors

IEEE electron device letters, 2018-09, Vol.39 (9), p.1282-1285

2018

Volltextzugriff (PDF)

Enhanced Performance of P-FET Omega-Gate SoI Nanowire With Recessed-SiGe Source-Drain Down to 13-nm Gate Length

IEEE electron device letters, 2013-09, Vol.34 (9), p.1103-1105

2013

Volltextzugriff (PDF)

3D spatial resolution improvement by dual-axis electron tomography: Application to tri-gate transistors

Ultramicroscopy, 2014-01, Vol.136, p.144-153

2014

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Scaling-aware TCAD Parameter Extraction Methodology for Mobility Prediction in Tri-gate Nanowire Transistors

2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2019, p.1-4

2019

Volltextzugriff (PDF)

The influence of Coulomb centers located in HfO 2 / SiO 2 gate stacks on the effective electron mobility

Journal of applied physics, 2008-10, Vol.104 (7), p.073725-073725-10

2008

Volltextzugriff (PDF)

A new method for junctionless transistors parameters extraction

2017 47th European Solid-State Device Research Conference (ESSDERC), 2017, p.66-69

2017

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New insight on the geometry dependence of BTI in 3D technologies based on experiments and modeling

2017 Symposium on VLSI Technology, 2017, p.T134-T135

2017

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From devices to circuits: modelling the performance of 5nm nanosheets

2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2019, p.1-4

2019

Volltextzugriff (PDF)

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Gate-based high fidelity spin readout in a CMOS device

Analysis of the Electrical Parameters of SOI Junctionless Nanowire Transistors at High Temperatures

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

Process Variability-Technological Challenge and Design Issue for Nanoscale Devices

Effects of channel width variation on electrical characteristics of tri-gate Junctionless transistors

Development of a CMOS Route for Electron Pumps to Be Used in Quantum Metrology

Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures

Bias dependent physics-based model of low-frequency noise for nanowire type gate-all-around MOSFETs

Impact of (Quasi-)Ballistic Transport on Operation of Complementary Metal–Oxide–Semiconductor Inverters Based on Fully-Depleted Silicon-on-Insulator and Nanowire Devices

Compact Analytical Model for Trap-Related Low Frequency Noise in Junctionless Transistors

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

Method for Extracting Doping Concentration and Flat-Band Voltage in Junctionless Multigate MOSFETs Using 2-D Electrostatic Effects

SET Sensitivity of Trigate Silicon Nanowire Field-Effect Transistors

Gate-based high fidelity spin readout in a CMOS device

Readout and control of the spin-orbit states of two coupled acceptor atoms in a silicon transistor

Evaluation and implementation of High-Dimensionnal Computing for gesture recognition using sEMG signals

Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K

A Simple Method for Estimation of Silicon Film Thickness in Tri-Gate Junctionless Transistors

Enhanced Performance of P-FET Omega-Gate SoI Nanowire With Recessed-SiGe Source-Drain Down to 13-nm Gate Length

3D spatial resolution improvement by dual-axis electron tomography: Application to tri-gate transistors

Scaling-aware TCAD Parameter Extraction Methodology for Mobility Prediction in Tri-gate Nanowire Transistors

The influence of Coulomb centers located in HfO 2 / SiO 2 gate stacks on the effective electron mobility

A new method for junctionless transistors parameters extraction

New insight on the geometry dependence of BTI in 3D technologies based on experiments and modeling

From devices to circuits: modelling the performance of 5nm nanosheets

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