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Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-12, Vol.41 (12), p.5515-5525

2022

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Accurate Recycled FPGA Detection Using an Exhaustive-Fingerprinting Technique Assisted by WID Process Variation Modeling

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-08, Vol.40 (8), p.1626-1639

2021

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Organic Current Mirror PUF for Improved Stability Against Device Aging

IEEE sensors journal, 2020-07, Vol.20 (14), p.7569-7578

2020

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Efficient Wafer-Level Spatial Variation Modeling for Multi-Site RF IC Testing

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2024-08, Vol.E107.A (8), p.1139-1150, Article 2023EAP1115

2024

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Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit

Journal of electronic testing, 2020-08, Vol.36 (4), p.537-546

2020

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Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2024-01, Vol.E107.A (1), p.96-104, Article 2023KEP0010

2024

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Feasibility of a low-power, low-voltage complementary organic thin film transistor buskeeper physical unclonable function

Japanese Journal of Applied Physics, 2019-04, Vol.58 (SB), p.SBBG03

2019

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Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2020-09, Vol.E103.A (9), p.1045-1053

2020

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Recovery-aware bias-stress degradation model for organic thin-film transistors considering drain and gate bias voltages

Japanese Journal of Applied Physics, 2020-04, Vol.59 (SG), p.SGGG08

2020

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Measurement and Modeling of Ambient-Air-Induced Degradation in Organic Thin-Film Transistor

IEEE transactions on semiconductor manufacturing, 2020-05, Vol.33 (2), p.216-223

2020

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Measurement and modeling of gate-drain capacitance of silicon carbide vertical double-diffused MOSFET

Japanese Journal of Applied Physics, 2017-04, Vol.56 (4S), p.4-04CR07

2017

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Artificial Neural Network Based Test Escape Screening Using Generative Model

2018 IEEE International Test Conference (ITC), 2018, p.1-8

2018

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Mechanically and electrically robust metal-mask design for organic CMOS circuits

Japanese Journal of Applied Physics, 2018-04, Vol.57 (4S), p.4

2018

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A compact model of I -V characteristic degradation for organic thin film transistors

2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS), 2019, p.194-199

2019

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Area-Efficient and Reliable Hybrid CMOS/Memristor ECC Circuit for ReRAM Storage

2018 IEEE 27th Asian Test Symposium (ATS), 2018, p.167-172

2018

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Hardware–Software Co-Design for Decimal Multiplication

Computers (Basel), 2021-02, Vol.10 (2), p.17

2021

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A Variability-Aware Adaptive Test Flow for Test Quality Improvement

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-07, Vol.33 (7), p.1056-1066

2014

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A high power curve tracer for characterizing full operational range of SiC power transistors

2016 International Conference on Microelectronic Test Structures (ICMTS), 2016, p.90-94

2016

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Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2017-01, Vol.E100.A (7), p.1464-1472

2017

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Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2016-07, Vol.E99.A (7), p.1400-1409

2016

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Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing

Journal of electronic testing, 2016-10, Vol.32 (5), p.601-609

2016

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IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination

IEICE Transactions on Information and Systems, 2014, Vol.E97.D(8), pp.2095-2104

2014

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Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control

2016 IEEE 25th Asian Test Symposium (ATS), 2016, p.234-239

2016

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Device-Parameter Estimation through IDDQ Signatures

IEICE Transactions on Information and Systems, 2013/02/01, Vol.E96.D(2), pp.303-313

2013

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Identification and Application of Invariant Critical Paths under NBTI Degradation

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2017-01, Vol.E100.A (12), p.2797-2806

2017

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Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation

Accurate Recycled FPGA Detection Using an Exhaustive-Fingerprinting Technique Assisted by WID Process Variation Modeling

Organic Current Mirror PUF for Improved Stability Against Device Aging

Efficient Wafer-Level Spatial Variation Modeling for Multi-Site RF IC Testing

Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit

Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects

Feasibility of a low-power, low-voltage complementary organic thin film transistor buskeeper physical unclonable function

Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework

Recovery-aware bias-stress degradation model for organic thin-film transistors considering drain and gate bias voltages

Measurement and Modeling of Ambient-Air-Induced Degradation in Organic Thin-Film Transistor

Measurement and modeling of gate-drain capacitance of silicon carbide vertical double-diffused MOSFET

Artificial Neural Network Based Test Escape Screening Using Generative Model

Mechanically and electrically robust metal-mask design for organic CMOS circuits

A compact model of I -V characteristic degradation for organic thin film transistors

Area-Efficient and Reliable Hybrid CMOS/Memristor ECC Circuit for ReRAM Storage

Hardware–Software Co-Design for Decimal Multiplication

A Variability-Aware Adaptive Test Flow for Test Quality Improvement

A high power curve tracer for characterizing full operational range of SiC power transistors

Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation

Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability

Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing

IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination

Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control

Device-Parameter Estimation through IDDQ Signatures

Identification and Application of Invariant Critical Paths under NBTI Degradation

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