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The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-12, Vol.27 (12), p.2209-2222

2008

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Constraint-Based Layout-Driven Sizing of Analog Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-08, Vol.30 (8), p.1089-1102

2011

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Pareto optimization of analog circuits considering variability

International journal of circuit theory and applications, 2009-03, Vol.37 (2), p.283-299

2009

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A CPPLL hierarchical optimization methodology considering jitter, power and locking time

2006 43rd ACM/IEEE Design Automation Conference, 2006, p.19-24

2006

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Hierarchical Analog Power-Down Synthesis

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2020, p.1-4

2020

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MARS: Matching-Driven Analog Sizing

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-08, Vol.31 (8), p.1145-1158

2012

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Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-02, Vol.30 (2), p.180-193

2011

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Mismatch analysis and direct yield optimization by spec-wise linearization and feasibility-guided search

Proceedings - ACM IEEE Design Automation Conference, 2001, p.858-863

2001

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ITRS 2011 Analog EDA Challenges and Approaches

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, p.1150-1155

Graeb, H.

2012

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Performance trade-off analysis of analog circuits by normal-boundary intersection

Annual ACM IEEE Design Automation Conference: Proceedings of the 40th conference on Design automation; 02-06 June 2003, 2003, p.958-963

2003

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Circuit analysis and optimization driven by worst-case distances

IEEE transactions on computer-aided design of integrated circuits and systems, 1994-01, Vol.13 (1), p.57-71

1994

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Analog testing by characteristic observation inference

IEEE transactions on computer-aided design of integrated circuits and systems, 1999-09, Vol.18 (9), p.1353-1368

1999

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Deterministic approaches to analog performance space exploration (PSE)

Annual ACM IEEE Design Automation Conference: Proceedings of the 42nd annual conference on Design automation; 13-17 June 2005, 2005, p.869-874

2005

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Analog circuit sizing using adaptive worst-case parameter sets

Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, 2002, p.581-585

2002

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Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-10, Vol.26 (10), p.1733-1748

2007

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Reliability analysis of analog circuits using quadratic lifetime worst-case distance prediction

IEEE Custom Integrated Circuits Conference 2010, 2010, p.1-4

2010

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The sizing rules method for analog integrated circuit design

Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design, 2001, p.343-349

2001

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A test design method for floating gate defects (FGD) in analog integrated circuits

Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, 2002, p.78-83

2002

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Automating the sizing of analog CMOS circuits by consideration of structural constraints

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), 1999, p.323-327

1999

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Sizing analog circuits using an SQP and Branch and Bound based approach

2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010, p.37-40

2010

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Analog layout synthesis - Recent advances in topological approaches

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009, p.274-279

2009

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Trade-Off Design of Analog Circuits using Goal Attainment and "Wave Front" Sequential Quadratic Programming

2007 Design, Automation & Test in Europe Conference & Exhibition, 2007, p.1-6

2007

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Formal approaches to analog circuit verification

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009, p.724-729

2009

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Sizing Rules for Bipolar Analog Circuit Design

2008 Design, Automation and Test in Europe, 2008, p.140-145

2008

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A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters

2008 IEEE International Conference on Computer Design, 2008, p.188-193

2008

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The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis

Constraint-Based Layout-Driven Sizing of Analog Circuits

Pareto optimization of analog circuits considering variability

A CPPLL hierarchical optimization methodology considering jitter, power and locking time

Hierarchical Analog Power-Down Synthesis

MARS: Matching-Driven Analog Sizing

Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits

Mismatch analysis and direct yield optimization by spec-wise linearization and feasibility-guided search

ITRS 2011 Analog EDA Challenges and Approaches

Performance trade-off analysis of analog circuits by normal-boundary intersection

Circuit analysis and optimization driven by worst-case distances

Analog testing by characteristic observation inference

Deterministic approaches to analog performance space exploration (PSE)

Analog circuit sizing using adaptive worst-case parameter sets

Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination

Reliability analysis of analog circuits using quadratic lifetime worst-case distance prediction

The sizing rules method for analog integrated circuit design

A test design method for floating gate defects (FGD) in analog integrated circuits

Automating the sizing of analog CMOS circuits by consideration of structural constraints

Sizing analog circuits using an SQP and Branch and Bound based approach

Analog layout synthesis - Recent advances in topological approaches

Trade-Off Design of Analog Circuits using Goal Attainment and "Wave Front" Sequential Quadratic Programming

Formal approaches to analog circuit verification

Sizing Rules for Bipolar Analog Circuit Design

A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters

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