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Measuring Holding Voltage Related to Homogeneous Current Flow in Wide ESD Protection Structures Using Multilevel TLP

IEEE transactions on electron devices, 2011-02, Vol.58 (2), p.411-418

2011

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System ESD robustness by co-design of on-chip and on-board protection measures

Microelectronics and reliability, 2010-09, Vol.50 (9), p.1359-1366

2010

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System efficient ESD design

Microelectronics and reliability, 2015-12, Vol.55 (12), p.2607-2613

2015

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Characterization and Optimization of Sub-32-nm FinFET Devices for ESD Applications

IEEE transactions on electron devices, 2008-12, Vol.55 (12), p.3507-3516

2008

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Advanced 2D/3D ESD device simulation – a powerful tool already used in a pre-Si phase

Microelectronics and reliability, 2001-11, Vol.41 (11), p.1761-1770

2001

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Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures

IEEE transactions on electron devices, 2012-05, Vol.59 (5), p.1353-1363

2012

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A Novel Drain-Extended FinFET Device for High-Voltage High-Speed Applications

IEEE electron device letters, 2012-10, Vol.33 (10), p.1432-1434

2012

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A Drain-Extended MOS Device With Spreading Filament Under ESD Stress

IEEE electron device letters, 2012-09, Vol.33 (9), p.1294-1296

2012

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ESD full chip simulation: HBM and CDM requirements and simulation approach

Advances in radio science, 2008-01, Vol.6 (1), p.245-251

2008

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Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

IEEE transactions on electron devices, 2010-02, Vol.57 (2), p.448-457

2010

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RF ESD protection strategies: Codesign vs. low- C protection

Microelectronics and reliability, 2007-07, Vol.47 (7), p.1008-1015

2007

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Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines

IEEE transactions on electron devices, 2011-06, Vol.58 (6), p.1597-1607

2011

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Part I: On the Behavior of STI-Type DeNMOS Device Under ESD Conditions

IEEE transactions on electron devices, 2010-09, Vol.57 (9), p.2235-2242

2010

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Part II: On the Three-Dimensional Filamentation and Failure Modeling of STI Type DeNMOS Device Under Various ESD Conditions

IEEE transactions on electron devices, 2010-09, Vol.57 (9), p.2243-2250

2010

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An Insight Into the ESD Behavior of the Nanometer-Scale Drain-Extended NMOS Device-Part I: Turn-On Behavior of the Parasitic Bipolar

IEEE transactions on electron devices, 2011-02, Vol.58 (2), p.309-317

2011

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An Insight Into ESD Behavior of Nanometer-Scale Drain Extended NMOS (DeNMOS) Devices: Part II (Two-Dimensional Study-Biasing & Comparison With NMOS)

IEEE transactions on electron devices, 2011-02, Vol.58 (2), p.318-326

2011

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High abstraction level permutational ESD concept analysis

Microelectronics and reliability, 2005-02, Vol.45 (2), p.313-321

2005

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Harnessing the base-pushout effect for ESD protection in bipolar and BiCMOS technologies

Microelectronics and reliability, 2003-07, Vol.43 (7), p.1001-1010

2003

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Part II: A Novel Scheme to Optimize the Mixed-Signal Performance and Hot-carrier Reliability of Drain-Extended MOS Devices

IEEE transactions on electron devices, 2010-02, Vol.57 (2), p.458-465

2010

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Interferometric temperature mapping during ESD stress and failure analysis of smart power technology ESD protection devices

Journal of electrostatics, 2000-08, Vol.49 (3), p.195-213

2000

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Excitonic luminescence from locally grown SiGe wires and dots

Applied physics letters, 1994-02, Vol.64 (8), p.994-996

1994

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Study of triggering inhomogeneities in gg-nMOS ESD protection devices via thermal mapping using backside laser interferometry

Microelectronics and reliability, 2000-08, Vol.40 (8-10), p.1359-1364

2000

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Case study of a technology transfer causing ESD problems

Microelectronics and reliability, 2002-09, Vol.42 (9), p.1275-1280

2002

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Measuring Holding Voltage Related to Homogeneous Current Flow in Wide ESD Protection Structures Using Multilevel TLP

IEEE transactions on electron devices, 2011, Vol.58 (2), p.411-418

2011

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Device Simulation and Backside Laser Interferometry––Powerful Tools for ESD Protection Development

Microelectronics and reliability, 2002-09, Vol.42 (9), p.1267-1274

2002

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Measuring Holding Voltage Related to Homogeneous Current Flow in Wide ESD Protection Structures Using Multilevel TLP

System ESD robustness by co-design of on-chip and on-board protection measures

System efficient ESD design

Characterization and Optimization of Sub-32-nm FinFET Devices for ESD Applications

Advanced 2D/3D ESD device simulation – a powerful tool already used in a pre-Si phase

Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures

A Novel Drain-Extended FinFET Device for High-Voltage High-Speed Applications

A Drain-Extended MOS Device With Spreading Filament Under ESD Stress

ESD full chip simulation: HBM and CDM requirements and simulation approach

Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

RF ESD protection strategies: Codesign vs. low- C protection

Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines

Part I: On the Behavior of STI-Type DeNMOS Device Under ESD Conditions

Part II: On the Three-Dimensional Filamentation and Failure Modeling of STI Type DeNMOS Device Under Various ESD Conditions

An Insight Into the ESD Behavior of the Nanometer-Scale Drain-Extended NMOS Device-Part I: Turn-On Behavior of the Parasitic Bipolar

An Insight Into ESD Behavior of Nanometer-Scale Drain Extended NMOS (DeNMOS) Devices: Part II (Two-Dimensional Study-Biasing & Comparison With NMOS)

High abstraction level permutational ESD concept analysis

Harnessing the base-pushout effect for ESD protection in bipolar and BiCMOS technologies

Part II: A Novel Scheme to Optimize the Mixed-Signal Performance and Hot-carrier Reliability of Drain-Extended MOS Devices

Interferometric temperature mapping during ESD stress and failure analysis of smart power technology ESD protection devices

Excitonic luminescence from locally grown SiGe wires and dots

Study of triggering inhomogeneities in gg-nMOS ESD protection devices via thermal mapping using backside laser interferometry

Case study of a technology transfer causing ESD problems

Measuring Holding Voltage Related to Homogeneous Current Flow in Wide ESD Protection Structures Using Multilevel TLP

Device Simulation and Backside Laser Interferometry––Powerful Tools for ESD Protection Development

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