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Effect of Sensing Film Thickness on Sensing Characteristics of Dual-Gate Poly-Si Ion-Sensitive Field-Effect-Transistors
IEEE electron device letters, 2014-12, Vol.35 (12), p.1302-1304
2014
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High-performance nonvolatile HfO2 nanocrystal memory
IEEE electron device letters, 2005-03, Vol.26 (3), p.154-156
2005
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Impact of Channel Dangling Bonds on Reliability Characteristics of Flash Memory on Poly-Si Thin Films
IEEE electron device letters, 2007-04, Vol.28 (4), p.267-269
2007
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Vertical n-Channel Poly-Si Thin-Film Transistors With Symmetric S/D Fabricated by Ni-Silicide-Induced Lateral-Crystallization Technology
IEEE electron device letters, 2009-03, Vol.30 (3), p.237-239
2009
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Poly-Si Thin-Film Transistor Nonvolatile Memory Using Ge Nanocrystals as a Charge Trapping Layer Deposited by the Low-Pressure Chemical Vapor Deposition
IEEE electron device letters, 2009-03, Vol.30 (3), p.234-236
2009
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Suppression of the floating-body effect in poly-Si thin-film transistors with self-aligned Schottky barrier source and ohmic body contact structure
IEEE electron device letters, 2004-09, Vol.25 (9), p.634-636
2004
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Characteristics of PBTI and Hot Carrier Stress for LTPS-TFT With High- \kappa Gate Dielectric
IEEE electron device letters, 2008-02, Vol.29 (2), p.171-173
2008
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Improvement of junction leakage of nickel silicided junction by a Ti-capping layer
IEEE electron device letters, 1999-11, Vol.20 (11), p.572-573
1999
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Impacts of Fluorine Ion Implantation With Low-Temperature Solid-Phase Crystallized Activation on High- \kappa LTPS-TFT
IEEE electron device letters, 2008-02, Vol.29 (2), p.168-170
2008
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Novel cleaning solutions for polysilicon film post chemical mechanical polishing
IEEE electron device letters, 2000-07, Vol.21 (7), p.338-340
2000
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Impacts of N2 and NH3 Plasma Surface Treatments on High-Performance LTPS-TFT With High-κ Gate Dielectric
IEEE electron device letters, 2008, Vol.29 (11), p.1236-1238
2008
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High-performance poly-Si TFTs with fully Ni-self-aligned silicided S/D and gate structure
IEEE electron device letters, 2006-04, Vol.27 (4), p.258-261
2006
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Performance and reliability of poly-Si TFTs on FSG buffer layer
IEEE electron device letters, 2005-07, Vol.26 (7), p.467-469
2005
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High-Performance Metal-Induced Laterally Crystallized Polycrystalline Silicon P-Channel Thin-Film Transistor With TaN/HfO2 Gate Stack Structure
IEEE electron device letters, 2008-06, Vol.29 (6), p.592-594
2008
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The impact of deep Ni salicidation and NH3 plasma treatment on nano-SOI FinFETs
IEEE electron device letters, 2006-10, Vol.27 (10), p.799-801
2006
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High-Performance Metal-Induced Laterally Crystallized Polycrystalline Silicon P-Channel Thin-Film Transistor With [Formula Omitted] Gate Stack Structure
IEEE electron device letters, 2008-06, Vol.29 (6), p.592-594
2008
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High-Performance Metal-Induced Laterally Crystallized Polycrystalline Silicon P-Channel Thin-Film Transistor With \hbox Gate Stack Structure
IEEE electron device letters, 2008-06, Vol.29 (6), p.592-594
2008
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Impact of High- \kappa Offset Spacer in 65-nm Node SOI Devices
IEEE electron device letters, 2007-03, Vol.28 (3), p.238-241
2007
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The Impact of Deep Ni Salicidation and Plasma Treatment on Nano-SOI FinFETs
IEEE electron device letters, 2006-10, Vol.27 (10), p.799
2006
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The Impact of Deep Ni Salicidation and hboxNH3Plasma Treatment on Nano-SOI FinFETs
IEEE electron device letters, 2006-10, Vol.27 (10), p.799-801
2006
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High-performance nonvolatile HfO/sub 2/ nanocrystal memory
IEEE electron device letters, 2005-03, Vol.26 (3), p.154-156
2005
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Impacts of Fluorine Ion Implantation With Low-Temperature Solid-Phase Crystallized Activation on High- [Formula Omitted] LTPS-TFT
IEEE electron device letters, 2008-02, Vol.29 (2), p.168-170
2008
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Characteristics of PBTI and Hot Carrier Stress for LTPS-TFT With High-[Formula Omitted] Gate Dielectric
IEEE electron device letters, 2008-02, Vol.29 (2), p.171-173
2008
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Improvement of low-temperature gate dielectric formed in N2O plasma by an additional CF4 pretreatment process
IEEE electron device letters, 2002-07, Vol.23 (7), p.389-391
2002
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Impact of High-[Formula Omitted] Offset Spacer in 65-nm Node SOI Devices
IEEE electron device letters, 2007-03, Vol.28 (3), p.238-241
2007
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