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A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL

IEEE journal of solid-state circuits, 2007-11, Vol.42 (11), p.2369-2377

2007

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Wide-range fast-lock duty-cycle corrector with offset-tolerant duty-cycle detection scheme for 54nm 7Gb/s GDDR5 DRAM interface

2009 Symposium on VLSI Circuits, 2009, p.138-139

2009

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A 1.5-V 3.2Gb/s/pin Graphic DDR4 SDRAM with Dual-Clock System, 4 Phase Input Strobing and Low Jitter Fully Analog DLL

2006 IEEE Asian Solid-State Circuits Conference, 2006, p.39-42

2006

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A Method of Determining the Equivalent Core Length of the Large Synchronous Motor With Radial Air Ducts

IEEE transactions on magnetics, 2017-06, Vol.53 (6), p.1-4

2017

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AlGaN/GaN Metal-Oxide-Semiconductor Heterojunction Field-Effect Transistor Integrated With Clamp Circuit to Enable Normally-Off Operation

IEEE electron device letters, 2015-06, Vol.36 (6), p.540-542

2015

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Low onset voltage of GaN on Si Schottky barrier diode using various recess depths

Electronics letters, 2014-07, Vol.50 (16), p.1164-1165

2014

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Effectiveness of a Guard Ring Utilizing an Inversion Layer Surrounding a Through Silicon Via

IEEE electron device letters, 2015-03, Vol.36 (3), p.268-270

2015

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A Small and Lightweight Antenna for Handheld RFID Reader Applications

IEEE antennas and wireless propagation letters, 2012, Vol.11, p.1076-1079

2012

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8Gb 3D DDR3 DRAM using through-silicon-via technology

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.130-131,131a

2009

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25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.346-348

2021

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A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.206-208

2018

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Design of Exhibition contents using swipe gesture recognition communication based on Kinect

2015 International Conference on Information Networking (ICOIN), 2015, p.346-347

2015

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A new guard-ring technique to reduce coupling noise from through silicon via (TSV) utilizing inversion charge induced by interface charge

2013 Symposium on VLSI Technology, 2013, p.T44-T45

2013

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Performance Prediction Process of Outer Rotor PMSM Through 3-D Flux Coefficient Using Equivalent 2-D FEA

2024 IEEE 21st Biennial Conference on Electromagnetic Field Computation (CEFC), 2024, p.1-2

2024

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Highly scalable Z-RAM with remarkably long data retention for DRAM application

2009 Symposium on VLSI Technology, 2009, p.234-235

2009

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3-Hop-ahead path reservation scheme for expedite traffic in wireless sensor networks

2009 International Conference on Information Networking, 2009, p.1-5

2009

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AC driven low pressure plasam reactor with annular shaped electrodes for abatement of pollutants emitted from semiconductor processing

2010 Abstracts IEEE International Conference on Plasma Science, 2010, p.1-1

2010

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A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process

2018 IEEE Symposium on VLSI Circuits, 2018, p.147-148

2018

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Equivalent core length consideration of synchronous motor with radial air-ducts by using 3D electromagnetic finite element method

2016 IEEE Conference on Electromagnetic Field Computation (CEFC), 2016, p.1-1

2016

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Sound source matching LED emotion contents design

2015 Seventh International Conference on Ubiquitous and Future Networks, 2015, p.372-374

2015

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Investigation on the axial magnetic field of cup type vacuum interrupter considering the geometry of contact support

2017 4th International Conference on Electric Power Equipment - Switching Technology (ICEPE-ST), 2017, p.183-186

2017

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Deriving High-Performance Real-Time Multicore Systems Based on Simulink Applications

2011 IEEE Ninth International Conference on Dependable, Autonomic and Secure Computing, 2011, p.267-274

2011

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Design of a w-band monopulse comparator based on E- and H-plane waveguide couplers

2010 IEEE 11th Annual Wireless and Microwave Technology Conference (WAMICON), 2010, p.1-5

2010

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Operating of industrial scale dielectric barrier discharge reactor for NO/sub x/ or odor control

The 30th International Conference on Plasma Science, 2003. ICOPS 2003. IEEE Conference Record - Abstracts, 2003, p.379

2003

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270-W 15-kHz MOPA system based on side-pumped rod-type Nd:YAG gain modules

2009 Conference on Lasers & Electro Optics & The Pacific Rim Conference on Lasers and Electro-Optics, 2009, p.1-2

2009

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A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL

Wide-range fast-lock duty-cycle corrector with offset-tolerant duty-cycle detection scheme for 54nm 7Gb/s GDDR5 DRAM interface

A 1.5-V 3.2Gb/s/pin Graphic DDR4 SDRAM with Dual-Clock System, 4 Phase Input Strobing and Low Jitter Fully Analog DLL

A Method of Determining the Equivalent Core Length of the Large Synchronous Motor With Radial Air Ducts

AlGaN/GaN Metal-Oxide-Semiconductor Heterojunction Field-Effect Transistor Integrated With Clamp Circuit to Enable Normally-Off Operation

Low onset voltage of GaN on Si Schottky barrier diode using various recess depths

Effectiveness of a Guard Ring Utilizing an Inversion Layer Surrounding a Through Silicon Via

A Small and Lightweight Antenna for Handheld RFID Reader Applications

8Gb 3D DDR3 DRAM using through-silicon-via technology

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

Design of Exhibition contents using swipe gesture recognition communication based on Kinect

A new guard-ring technique to reduce coupling noise from through silicon via (TSV) utilizing inversion charge induced by interface charge

Performance Prediction Process of Outer Rotor PMSM Through 3-D Flux Coefficient Using Equivalent 2-D FEA

Highly scalable Z-RAM with remarkably long data retention for DRAM application

3-Hop-ahead path reservation scheme for expedite traffic in wireless sensor networks

AC driven low pressure plasam reactor with annular shaped electrodes for abatement of pollutants emitted from semiconductor processing

A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process

Equivalent core length consideration of synchronous motor with radial air-ducts by using 3D electromagnetic finite element method

Sound source matching LED emotion contents design

Investigation on the axial magnetic field of cup type vacuum interrupter considering the geometry of contact support

Deriving High-Performance Real-Time Multicore Systems Based on Simulink Applications

Design of a w-band monopulse comparator based on E- and H-plane waveguide couplers

Operating of industrial scale dielectric barrier discharge reactor for NO/sub x/ or odor control

270-W 15-kHz MOPA system based on side-pumped rod-type Nd:YAG gain modules

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