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A 0.9-μm² 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming

IEEE journal of solid-state circuits, 2017-04, Vol.52 (4), p.933-939

2017

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A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology

IEEE journal of solid-state circuits, 2009-01, Vol.44 (1), p.148-154

2009

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Design and optimization of low voltage high performance dual threshold CMOS circuits

Annual ACM IEEE Design Automation Conference: Proceedings of the 35th annual conference on Design automation; 15-19 June 1998, 1998, p.489-494

1998

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A 0.9-μ² 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming

IEEE journal of solid-state circuits, 2017-01, Vol.52 (4), p.933

2017

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A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.136-137

2022

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Mixed-Vth (MVT) CMOS circuit design methodology for low power applications

Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 1999, p.430-435

1999

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On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques

IEEE transactions on very large scale integration (VLSI) systems, 2001-09, Vol.9 (5), p.718-725

2001

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A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 mu m 2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS

IEEE journal of solid-state circuits, 2010-04, Vol.45 (1-4), p.863-868

2010

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A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 [Formula Omitted]m[Formula Omitted] 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.863-868

2010

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Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors

International Symposium on Low Power Electronics and Design: Proceedings of the 2001 international symposium on Low power electronics and design, 2001, p.147-152

2001

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A 1.1 GHz 12 \muA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.172-179

2008

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A 32nm high-k and metal-gate anti-fuse array featuring a 1.01µm2 1T1C bit cell

2012 Symposium on VLSI Technology (VLSIT), 2012, p.79-80

2012

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A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μm2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS

IEEE journal of solid-state circuits, 2010, Vol.45 (4), p.863-868

2010

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Power sensitivity-a new method to estimate power dissipation considering uncertain specifications of primary inputs

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), 1997, p.40-44

1997

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On effective I(DDQ) testing of low-voltage CMOS circuits using leakage control techniques

IEEE transactions on very large scale integration (VLSI) systems, 2001-10, Vol.9 (5), p.718-725

2001

Volltextzugriff (PDF)

On effective I sub(DDQ) testing of low-voltage CMOS circuits using leakage control techniques

IEEE transactions on very large scale integration (VLSI) systems, 2001-10, Vol.9 (5), p.718-725

2001

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Mixed-V sub(th) (MVT) CMOS circuit design methodology for low power applications

Proceedings - ACM IEEE Design Automation Conference, 1999-01

1999

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Gene interference regulates aquaporin-4 expression in swollen tissue of rats with cerebral ischemic edema Correlation with variation in apparent diffusion coefficient

Neural regeneration research, 2012-07, Vol.7 (21), p.1659-1666

2012

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Design and optimization of dual-threshold circuits for low-voltage low-power applications : Special section on low-power electronics and design

IEEE transactions on very large scale integration (VLSI) systems, 1999, Vol.7 (1), p.16-24

1999

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Therapeutic imaging window of cerebral infarction revealed by multisequence magnetic resonance imaging An animal and clinical study

Neural regeneration research, 2012-11, Vol.7 (31), p.2446-2455

2012

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Double gate dynamic threshold voltage (DGDT) SOI MOSFETs for low power high performance designs

1997 IEEE International SOI Conference Proceedings, 1997, p.82-83

1997

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A power macromodeling technique based on power sensitivity

Annual ACM IEEE Design Automation Conference: Proceedings of the 35th annual conference on Design automation; 15-19 June 1998, 1998, p.678-683

1998

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High-density 3-D metal-fuse PROM featuring 1.37µm2 1T1R bit cell in 32nm high-k metal-gate CMOS technology

2009 Symposium on VLSI Circuits, 2009, p.28-29

2009

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On effective I/sub DDQ/ testing of low voltage CMOS circuits using leakage control techniques

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525), 2000, p.181-188

2000

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Multiple-V/sub dd/ multiple-V/sub th/ CMOS (MVCMOS) for low power applications

1999 IEEE International Symposium on Circuits and Systems (ISCAS), 1999, Vol.1, p.366-370 vol.1

1999

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A 0.9-μm² 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming

A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology

Design and optimization of low voltage high performance dual threshold CMOS circuits

A 0.9-μ² 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming

A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology

Mixed-Vth (MVT) CMOS circuit design methodology for low power applications

On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques

A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 mu m 2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS

A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 [Formula Omitted]m[Formula Omitted] 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS

Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors

A 1.1 GHz 12 \muA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

A 32nm high-k and metal-gate anti-fuse array featuring a 1.01µm2 1T1C bit cell

A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μm2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS

Power sensitivity-a new method to estimate power dissipation considering uncertain specifications of primary inputs

On effective I(DDQ) testing of low-voltage CMOS circuits using leakage control techniques

On effective I sub(DDQ) testing of low-voltage CMOS circuits using leakage control techniques

Mixed-V sub(th) (MVT) CMOS circuit design methodology for low power applications

Gene interference regulates aquaporin-4 expression in swollen tissue of rats with cerebral ischemic edema Correlation with variation in apparent diffusion coefficient

Design and optimization of dual-threshold circuits for low-voltage low-power applications : Special section on low-power electronics and design

Therapeutic imaging window of cerebral infarction revealed by multisequence magnetic resonance imaging An animal and clinical study

Double gate dynamic threshold voltage (DGDT) SOI MOSFETs for low power high performance designs

A power macromodeling technique based on power sensitivity

High-density 3-D metal-fuse PROM featuring 1.37µm2 1T1R bit cell in 32nm high-k metal-gate CMOS technology

On effective I/sub DDQ/ testing of low voltage CMOS circuits using leakage control techniques

Multiple-V/sub dd/ multiple-V/sub th/ CMOS (MVCMOS) for low power applications

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