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Approximate computing and the quest for computing efficiency

Proceedings of the 52nd Annual Design Automation Conference, 2015, p.1-6

2015

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Quality programmable vector processors for approximate computing

2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2013, p.1-12

2013

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AQuA: Analytical Quality Assessment for Optimizing Video Analytics Systems

2021 IEEE/ACM Symposium on Edge Computing (SEC), 2021, p.135-147

2021

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Computing approximately, and efficiently

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, p.748-751

2015

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IEEE_Xplore

A Massively Parallel, Energy Efficient Programmable Accelerator for Learning and Classification

ACM transactions on architecture and code optimization, 2012-03, Vol.9 (1), p.1-30

2012

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Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC

2006 43rd ACM/IEEE Design Automation Conference, 2006, p.496-501

2006

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IEEE_Xplore

Static compaction using overlapped restoration and segment pruning

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287), 1998, p.140-146

1998

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IEEE_Xplore

Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling

ACM transactions on embedded computing systems, 2013-05, Vol.12 (2s), p.1-23

2013

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Tarazu: optimizing MapReduce on heterogeneous clusters

Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems, 2012, p.61-74

2012

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Testable Path Delay Fault Cover for Sequential Circuits

Journal of Information Science and Engineering, 2000-09, Vol.16 (5), p.673-686

2000

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Elixir: A System to Enhance Data Quality for Multiple Analytics on a Video Stream

2023 IEEE International Conference on Smart Computing (SMARTCOMP), 2023, p.98-107

2023

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Finite state machine synthesis with fault tolerant test function

Journal of electronic testing, 1993-02, Vol.4 (1), p.57-69

1993

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Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor

2008 Design, Automation and Test in Europe, 2008, p.1148-1153

2008

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IEEE_Xplore

Power monitors: a framework for system-level power estimation using heterogeneous power models

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, 2005, p.579-585

2005

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IEEE_Xplore

Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs

2006 15th Asian Test Symposium, 2006, p.339-348

2006

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IEEE_Xplore

Unknown Blocking Scheme for Low Control Data Volume and High Observability

2007 Design, Automation & Test in Europe Conference & Exhibition, 2007, p.1-6

2007

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IEEE_Xplore

PIDISC: pattern independent design independent seed compression technique

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006, p.7 pp.

2006

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IEEE_Xplore

A low cost test data compression technique for high n-detection fault coverage

2007 IEEE International Test Conference, 2007, p.1-10

2007

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IEEE_Xplore

Efficient Unknown Blocking Using LFSR Reseeding

Proceedings of the Design Automation & Test in Europe Conference, 2006, Vol.1, p.1-2

2006

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IEEE_Xplore

XWRC: externally-loaded weighted random pattern testing for input test data compression

IEEE International Conference on Test, 2005, 2005, p.10 pp.-580

2005

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IEEE_Xplore

Distance restricted scan chain reordering to enhance delay fault coverage

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, 2005, p.471-478

2005

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IEEE_Xplore

Zero Cost Test Point Insertion Technique for Structured ASICs

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007, p.357-363

2007

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IEEE_Xplore

Tarazu: optimizing MapReduce on heterogeneous clusters

SIGPLAN notices, 2012-06, Vol.47 (4), p.61-74

2012

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A synthesis approach to design for testability

Designing, testing, and diagnostics--join them : International Test Conference 1993 proceedings :October 17-21, 1993, Convention Center, Baltimore, Maryland, USA, 1993, p.754-763

1993

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IEEE_Xplore

Automatic test generation using quadratic 0-1 programming

Annual ACM IEEE Design Automation Conference: Proceedings of the 27th ACM/IEEE conference on Design automation; 24-27 June 1990, 1991, p.654-659

1991

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Approximate computing and the quest for computing efficiency

Quality programmable vector processors for approximate computing

AQuA: Analytical Quality Assessment for Optimizing Video Analytics Systems

Computing approximately, and efficiently

A Massively Parallel, Energy Efficient Programmable Accelerator for Learning and Classification

Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC

Static compaction using overlapped restoration and segment pruning

Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling

Tarazu: optimizing MapReduce on heterogeneous clusters

Testable Path Delay Fault Cover for Sequential Circuits

Elixir: A System to Enhance Data Quality for Multiple Analytics on a Video Stream

Finite state machine synthesis with fault tolerant test function

Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor

Power monitors: a framework for system-level power estimation using heterogeneous power models

Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs

Unknown Blocking Scheme for Low Control Data Volume and High Observability

PIDISC: pattern independent design independent seed compression technique

A low cost test data compression technique for high n-detection fault coverage

Efficient Unknown Blocking Using LFSR Reseeding

XWRC: externally-loaded weighted random pattern testing for input test data compression

Distance restricted scan chain reordering to enhance delay fault coverage

Zero Cost Test Point Insertion Technique for Structured ASICs

Tarazu: optimizing MapReduce on heterogeneous clusters

A synthesis approach to design for testability

Automatic test generation using quadratic 0-1 programming

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