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Self-selective van der Waals heterostructures for large scale memory array

Nature communications, 2019-07, Vol.10 (1), p.3161-7, Article 3161

2019

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In-sensor reservoir computing for language learning via two-dimensional memristors

Science advances, 2021-05, Vol.7 (20)

2021

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Adding Distance Information to Self-Supervised Learning for rich Representations

2023 IEEE International Conference on Image Processing (ICIP), 2023, p.1270-1274

2023

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High-Efficiency DC–DC Converter with Charge-Recycling Gate-Voltage Swing Control

Energies (Basel), 2019-03, Vol.12 (5), p.899

2019

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A Polymorphic Memtransistor with Tunable Metallic and Semiconducting Channel

Advanced materials (Weinheim), 2023-04, Vol.35 (15), p.e2209089-n/a

2023

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Double-sampled ΔΣ modulator with 1.5-bit FIR feedback DAC for reduced noise folding and increased power efficiency

Electronics letters, 2016-04, Vol.52 (8), p.598-600

2016

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10T SRAM Using Half- V} Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage

IEEE transactions on very large scale integration (VLSI) systems, 2017-04, Vol.25 (4), p.1193-1203

2017

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Charge sharing write driver and half‐VDD pre‐charge 8T SRAM with virtual ground for low‐power write and read operation

IET circuits, devices & systems, 2018-01, Vol.12 (1), p.94-98

2018

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A fast response integrated current-sensing circuit for peak-current-mode buck regulator

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC), 2014, p.155-158

2014

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A Fast Response Integrated Current-Sensing Circuit for Peak-Current-Mode Buck Regulator

Journal of semiconductor technology and science, 2014-12, Vol.14 (6), p.810-817

2014

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Memristance drift avoidance with charge bouncing for memristor-based nonvolatile memories

Journal of the Korean Physical Society, 2012, 61(9), , pp.1418-1421

2012

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A Single-Phase Contention-and Redundant Transition-Free Flip-Flop With Improved DQ Latency

IEEE journal of solid-state circuits, 2024-10, p.1-12

2024

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RRAM-Based Spiking Neural Network with Target-Modulated Spike-Timing-Dependent Plasticity

IEEE transactions on biomedical circuits and systems, 2024-08, Vol.PP, p.1-9

2024

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Crosstalk cancellation for frame memory bus on TV main boards

2016 IEEE 6th International Conference on Consumer Electronics - Berlin (ICCE-Berlin), 2016, p.100-103

2016

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10.4 A 5.8Gb/s adaptive integrating duobinary-based DFE receiver for multi-drop memory interface

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3

2015

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Widely Tunable Adaptive Resolution-controlled Read-sensing Reference Current Generation for Reliable PRAM Data Read at Scaled Technologies

Journal of semiconductor technology and science, 2017, Vol.17 (3), p.363-369

2017

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CMOS charge pump with separated charge sharing for improved boosting ratio and relaxed timing restriction

2011 9th IEEE International Conference on ASIC, 2011, p.133-136

2011

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Ultra-fast Adaptive Frequency-controlled Hysteretic Buck Converter for Portable Devices

Journal of semiconductor technology and science, 2016, Vol.16 (5), p.615-623

2016

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A Power-and Area-Efficient DFE Receiver with Tap Coefficient-rotating Summer for IoT Applications

2021 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia), 2021, p.1-4

2021

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A 6 Gbps/pin Low-Power Half-Duplex Active Cross-Coupled LVDS Transceiver with Switched Termination

ETRI journal, 2008-02, Vol.30 (4), p.612-614

2008

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Dynamic Differential Flip-Flop without Explicit Output Latching Stage for High-Speed SoC

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2021, p.1-4

2021

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Charge sharing write driver and half‐ pre‐charge 8T SRAM with virtual ground for low‐power write and read operation

IET circuits, devices & systems, 2018-01, Vol.12 (1), p.94-98

2018

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Charge sharing write driver and half-$V_{{\rm DD}}$VDD pre-charge 8T SRAM with virtual ground for low-power write and read operation

IET circuits, devices & systems, 2018-01, Vol.12 (1), p.94-98

2018

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Current-Integrating DFE with Sub-UI ISI Cancellation for Multi-Drop Channels

Journal of semiconductor technology and science, 2016, Vol.16 (1), p.112-117

2016

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Dual edge-triggered flip-flop with modified NAND keeper for high-performance VLSI

Current applied physics, 2004-02, Vol.4 (1), p.49-53

2004

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Self-selective van der Waals heterostructures for large scale memory array

In-sensor reservoir computing for language learning via two-dimensional memristors

Adding Distance Information to Self-Supervised Learning for rich Representations

High-Efficiency DC–DC Converter with Charge-Recycling Gate-Voltage Swing Control

A Polymorphic Memtransistor with Tunable Metallic and Semiconducting Channel

Double-sampled ΔΣ modulator with 1.5-bit FIR feedback DAC for reduced noise folding and increased power efficiency

10T SRAM Using Half- V} Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage

Charge sharing write driver and half‐VDD pre‐charge 8T SRAM with virtual ground for low‐power write and read operation

A fast response integrated current-sensing circuit for peak-current-mode buck regulator

A Fast Response Integrated Current-Sensing Circuit for Peak-Current-Mode Buck Regulator

Memristance drift avoidance with charge bouncing for memristor-based nonvolatile memories

A Single-Phase Contention-and Redundant Transition-Free Flip-Flop With Improved DQ Latency

RRAM-Based Spiking Neural Network with Target-Modulated Spike-Timing-Dependent Plasticity

Crosstalk cancellation for frame memory bus on TV main boards

10.4 A 5.8Gb/s adaptive integrating duobinary-based DFE receiver for multi-drop memory interface

Widely Tunable Adaptive Resolution-controlled Read-sensing Reference Current Generation for Reliable PRAM Data Read at Scaled Technologies

CMOS charge pump with separated charge sharing for improved boosting ratio and relaxed timing restriction

Ultra-fast Adaptive Frequency-controlled Hysteretic Buck Converter for Portable Devices

A Power-and Area-Efficient DFE Receiver with Tap Coefficient-rotating Summer for IoT Applications

A 6 Gbps/pin Low-Power Half-Duplex Active Cross-Coupled LVDS Transceiver with Switched Termination

Dynamic Differential Flip-Flop without Explicit Output Latching Stage for High-Speed SoC

Charge sharing write driver and half‐ pre‐charge 8T SRAM with virtual ground for low‐power write and read operation

Charge sharing write driver and half-$V_{{\rm DD}}$VDD pre-charge 8T SRAM with virtual ground for low-power write and read operation

Current-Integrating DFE with Sub-UI ISI Cancellation for Multi-Drop Channels

Dual edge-triggered flip-flop with modified NAND keeper for high-performance VLSI

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