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Revisiting RowHammer: an experimental analysis of modern DRAM devices and mitigation techniques

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.638-651

2020

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New attacks and defense for encrypted-address cache

2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA), 2019, p.360-371

Qureshi, Moinuddin K.

2019

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Hardware architecture and software stack for PIM based on commercial DRAM technology

Proceedings of the 48th Annual International Symposium on Computer Architecture, 2021, p.43-56

2021

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An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013, p.60-71

2013

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QUAC-TRNG: high-throughput true random number generation using quadruple row activation in commodity DRAM chips

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), 2021, p.944-957

2021

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IEEE_Xplore

MuonTrap: preventing cross-domain spectre-like attacks by capturing speculative state

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.132-144

2020

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Uncovering In-DRAM RowHammer Protection Mechanisms:A New Methodology, Custom RowHammer Patterns, and Implications

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021, p.1198-1213

2021

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A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021, p.1182-1197

2021

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A new stochastic computing multiplier with application to deep convolutional neural networks

2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 2017, p.1-6

2017

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The reach profiler (REAPER): Enabling the mitigation of DRAM retention failures via profiling at aggressive conditions

2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017, p.255-268

2017

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TWiCe: preventing row-hammering by exploiting time window counters

2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA), 2019, p.385-396

2019

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IEEE_Xplore

A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS

2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, p.1-2

2024

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IEEE_Xplore

CLR-DRAM: a low-cost DRAM architecture enabling dynamic capacity-latency trade-off

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.666-679

2020

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Random Fill Cache Architecture

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014, p.203-215

2014

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IEEE_Xplore

Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology

2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2017, p.273-287

2017

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IEEE_Xplore

Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6

2016

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A 6-bit 10-GS/s 17.6-mW CMOS ADC with 0.8-V supply

2023 IEEE Custom Integrated Circuits Conference (CICC), 2023, p.1-2

2023

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IEEE_Xplore

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013, p.48-59

2013

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Bouquet of instruction pointers: instruction pointer classifier-based spatial hardware prefetching

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.118-131

2020

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A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes

2022 IEEE Custom Integrated Circuits Conference (CICC), 2022, p.1-2

2022

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IEEE_Xplore

Perceptron-based prefetch filtering

2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA), 2019, p.1-13

2019

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IEEE_Xplore

34.4 A Cryogenic Controller IC for Superconducting Qubits with DRAG Pulse Generation by Direct Synthesis without Using Memory

2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023, p.33-35

2023

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IEEE_Xplore

GraphQ: Scalable PIM-Based Graph Processing

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019, p.712-725

2019

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Equivalence among stochastic logic circuits and its application

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6

2015

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IEEE_Xplore

Die Stacking (3D) Microarchitecture

2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06), 2006, p.469-479

2006

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IEEE_Xplore

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Revisiting RowHammer: an experimental analysis of modern DRAM devices and mitigation techniques

New attacks and defense for encrypted-address cache

Hardware architecture and software stack for PIM based on commercial DRAM technology

An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms

QUAC-TRNG: high-throughput true random number generation using quadruple row activation in commodity DRAM chips

MuonTrap: preventing cross-domain spectre-like attacks by capturing speculative state

Uncovering In-DRAM RowHammer Protection Mechanisms:A New Methodology, Custom RowHammer Patterns, and Implications

A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses

A new stochastic computing multiplier with application to deep convolutional neural networks

The reach profiler (REAPER): Enabling the mitigation of DRAM retention failures via profiling at aggressive conditions

TWiCe: preventing row-hammering by exploiting time window counters

A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS

CLR-DRAM: a low-cost DRAM architecture enabling dynamic capacity-latency trade-off

Random Fill Cache Architecture

Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology

Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks

A 6-bit 10-GS/s 17.6-mW CMOS ADC with 0.8-V supply

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

Bouquet of instruction pointers: instruction pointer classifier-based spatial hardware prefetching

A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes

Perceptron-based prefetch filtering

34.4 A Cryogenic Controller IC for Superconducting Qubits with DRAG Pulse Generation by Direct Synthesis without Using Memory

GraphQ: Scalable PIM-Based Graph Processing

Equivalence among stochastic logic circuits and its application

Die Stacking (3D) Microarchitecture

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