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Small Sampling Overhead Error Mitigation for Quantum Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-03, Vol.43 (3), p.1-1

2024

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Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis

2023 IEEE International Test Conference (ITC), 2023, p.293-302

2023

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DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-01, Vol.38 (1), p.136-148

2019

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High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns

2023 IEEE International Test Conference (ITC), 2023, p.206-215

2023

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Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis

IEEE transactions on computers, 2007-03, Vol.56 (3), p.402-414

2007

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A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-07, Vol.35 (7), p.1130-1137

2016

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A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores

IEEE transactions on very large scale integration (VLSI) systems, 2012-01, Vol.20 (1), p.126-134

2012

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Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2014-03, Vol.22 (3), p.667-674

2014

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Transient IR-Drop Analysis for At-Speed Testing Using Representative Random Walk

IEEE transactions on very large scale integration (VLSI) systems, 2014-09, Vol.22 (9), p.1980-1989

2014

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Test Clock Domain Optimization to Avoid Scan Shift Failure Due to Flip-Flop Simultaneous Triggering

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-04, Vol.32 (4), p.644-652

2013

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Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-11, Vol.24 (11), p.1748-1759

2005

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Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits

2015 IEEE 24th Asian Test Symposium (ATS), 2015, p.181-186

2015

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Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

ACM transactions on design automation of electronic systems, 2012-10, Vol.17 (4), p.1-16

2012

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Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization

2021 IEEE International Test Conference (ITC), 2021, p.251-259

2021

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ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption

2022 IEEE International Test Conference (ITC), 2022, p.213-218

2022

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Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-01, Vol.33 (1), p.24-35

2014

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Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2016, Vol.E99.A (12), p.2320-2327

2016

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Test Pattern Modification for Average IR-Drop Reduction

IEEE transactions on very large scale integration (VLSI) systems, 2016-01, Vol.24 (1), p.38-49

2016

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Compact Test Pattern Selection for Small Delay Defect

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-06, Vol.32 (6), p.971-975

2013

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A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-11, Vol.30 (11), p.1767-1772

2011

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Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis

IEEE transactions on computers, 2012-07, Vol.61 (7), p.928-938

2012

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Test Pattern Compression for Probabilistic Circuits

2017 IEEE 26th Asian Test Symposium (ATS), 2017, p.23-27

2017

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A Flexible TFT Circuit Yield Optimizer Considering Process Variation, Aging, and Bending Effects

Journal of display technology, 2014-12, Vol.10 (12), p.1055-1063

2014

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An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology

Journal of electronic testing, 2011-04, Vol.27 (2), p.193-201

2011

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An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example

IEEE transactions on circuits and systems. I, Regular papers, 2012-08, Vol.59 (8), p.1644-1655

2012

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Small Sampling Overhead Error Mitigation for Quantum Circuits

Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis

DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG

High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns

Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis

A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse

A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores

Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits

Transient IR-Drop Analysis for At-Speed Testing Using Representative Random Walk

Test Clock Domain Optimization to Avoid Scan Shift Failure Due to Flip-Flop Simultaneous Triggering

Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs

Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization

ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption

Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics

Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration

Test Pattern Modification for Average IR-Drop Reduction

Compact Test Pattern Selection for Small Delay Defect

A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives

Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis

Test Pattern Compression for Probabilistic Circuits

A Flexible TFT Circuit Yield Optimizer Considering Process Variation, Aging, and Bending Effects

An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology

An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example

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