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Adaptive parallel decision deep neural network for high-speed equalization

Optics express, 2023-06, Vol.31 (13), p.22001-22011

2023

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A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication

IEEE access, 2022, Vol.10, p.96556-96567

2022

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A Fast Hierarchical Arbitration in Optical Network-on-Chip Based on Multi-Level Priority QoS

IEICE transactions on communications, 2016-04, Vol.E99.B (4), p.875-884

2016

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Co-packaged optics (CPO): status, challenges, and solutions

Frontiers of Optoelectronics (Online), 2023-03, Vol.16 (1), p.1-1, Article 1

2023

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Optimize the Power Consumption and SNR of the 3D Photonic High-Radix Switch Architecture Based on Extra Channels and Redundant Rings

Journal of Computer Networks and Communications, 2018-01, Vol.2018 (2018), p.1-8

2018

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Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs

IEEE transactions on computers, 2014-03, Vol.63 (3), p.529-542

2014

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P3Stor： A parallel, durable flash-based SSD for enterprise-scale storage systems

Science China. Information sciences, 2011-06, Vol.54 (6), p.1129-1141

2011

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An accurate and highly-efficient performance evaluation approach based on queuing model for on-chip network

Science China. Information sciences, 2013-07, Vol.56 (7), p.235-254

2013

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Two-level tries: A general acceleration structure for parallel routing table accesses

Journal of Communications and Networks, 2011, 13(4), , pp.408-417

2011

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A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment

IEEE journal of solid-state circuits, 2024-11, p.1-14

2024

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Crosstalk suppression for high-density traveling-wave MZM array based on static and dynamic combined analysis and circuit-level designs

Optics express, 2022-07, Vol.30 (15), p.27333-27345

2022

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An Electro-Optic Mixed Structure Multiplier with an Optical Delay Accumulation Scheme in Time-Domain

Journal of lightwave technology, 2024-05, Vol.42 (10), p.3786-3798

2024

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An Adaptive 56-Gb/s Duo-PAM4 Detector Using Reduced Branch Maximum Likelihood Sequence Detection in a 28-nm CMOS Wireline Receiver

IEEE transactions on circuits and systems. I, Regular papers, 2024-09, p.1-12

2024

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A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs

Microelectronics, 2024-10, Vol.152, p.106330, Article 106330

2024

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A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface

Microelectronics, 2024-10, Vol.152, p.106326, Article 106326

2024

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A Unified Clock-Gated Error Correction Scheme with Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router

IEEE transactions on circuits and systems. II, Express briefs, 2023-10, Vol.70 (10), p.1-1

2023

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A scalable smart router architecture with intelligent adaptive routing and fault-tolerant management

Neurocomputing (Amsterdam), 2020-06, Vol.393, p.126-141

2020

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A high speed and low BER dual-mode adaptive equalizer using hybrid parallel DFE

IEICE Electronics Express, 2024-10, Vol.21 (19), p.20240417-20240417, Article 21.20240417

2024

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Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator

IEEE transactions on circuits and systems. II, Express briefs, 2024-01, Vol.71 (1), p.1-1

2024

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A Metastability Inference and Avoidance Technique for Near-Threshold-Voltage Network-on-Chip

2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5

2023

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A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology

Microelectronics, 2023-10, Vol.140, p.105905, Article 105905

2023

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A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers

2008 45th ACM/IEEE Design Automation Conference, 2008, p.630-633

2008

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A TLP approach for BGP based on local speculation

Science China. Information sciences, 2008-11, Vol.51 (11), p.1772-1784

2008

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Optimization of TDM Using Single-ended Transmission for Multi-FPGA Platforms

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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A Cryo-CMOS, Low-Power, Low-Noise, Phase-Locked Loop Design for Quantum Computers

Electronics (Basel), 2023-08, Vol.12 (15), p.3237

2023

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Adaptive parallel decision deep neural network for high-speed equalization

A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication

A Fast Hierarchical Arbitration in Optical Network-on-Chip Based on Multi-Level Priority QoS

Co-packaged optics (CPO): status, challenges, and solutions

Optimize the Power Consumption and SNR of the 3D Photonic High-Radix Switch Architecture Based on Extra Channels and Redundant Rings

Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs

P3Stor： A parallel, durable flash-based SSD for enterprise-scale storage systems

An accurate and highly-efficient performance evaluation approach based on queuing model for on-chip network

Two-level tries: A general acceleration structure for parallel routing table accesses

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment

Crosstalk suppression for high-density traveling-wave MZM array based on static and dynamic combined analysis and circuit-level designs

An Electro-Optic Mixed Structure Multiplier with an Optical Delay Accumulation Scheme in Time-Domain

An Adaptive 56-Gb/s Duo-PAM4 Detector Using Reduced Branch Maximum Likelihood Sequence Detection in a 28-nm CMOS Wireline Receiver

A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs

A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface

A Unified Clock-Gated Error Correction Scheme with Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router

A scalable smart router architecture with intelligent adaptive routing and fault-tolerant management

A high speed and low BER dual-mode adaptive equalizer using hybrid parallel DFE

Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator

A Metastability Inference and Avoidance Technique for Near-Threshold-Voltage Network-on-Chip

A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology

A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers

A TLP approach for BGP based on local speculation

Optimization of TDM Using Single-ended Transmission for Multi-FPGA Platforms

A Cryo-CMOS, Low-Power, Low-Noise, Phase-Locked Loop Design for Quantum Computers

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