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Performance Enhancement of SMR-Based Deduplication Systems
IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.2835-2848
2022
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When Storage Response Time Catches Up With Overall Context Switch Overhead, What Is Next?
IEEE transactions on computer-aided design of integrated circuits and systems, 2020-11, Vol.39 (11), p.4266-4277
2020
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Energy Efficiency Enhancement of SCM-based Systems: Write-friendly Coding
IEEE transactions on computer-aided design of integrated circuits and systems, 2023-05, Vol.42 (5), p.1-1
2023
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iCheck: Progressive Checkpointing for Intermittent Systems
IEEE transactions on computer-aided design of integrated circuits and systems, 2021-11, Vol.40 (11), p.2224-2236
2021
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DeepPrefetcher: A Deep Learning Framework for Data Prefetching in Flash Storage Devices
IEEE transactions on computer-aided design of integrated circuits and systems, 2020-11, Vol.39 (11), p.3311-3322
2020
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Exploring Synchronous Page Fault Handling
IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.1-1
2022
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Beyond Address Mapping: A User-Oriented Multiregional Space Management Design for 3-D NAND Flash Memory
IEEE transactions on computer-aided design of integrated circuits and systems, 2020-06, Vol.39 (6), p.1286-1299
2020
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Leveraging Write Heterogeneity of Phase Change Memory on Supporting Self-Balancing Binary Tree
IEEE transactions on computer-aided design of integrated circuits and systems, 2022-06, Vol.41 (6), p.1757-1770
2022
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Hot-Spot Suppression for Resource-Constrained Image Recognition Devices With Nonvolatile Memory
IEEE transactions on computer-aided design of integrated circuits and systems, 2018-11, Vol.37 (11), p.2567-2577
2018
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On Improving the Write Responsiveness for Host-Aware SMR Drives
IEEE transactions on computers, 2019-01, Vol.68 (1), p.111-124
2019
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On Minimizing Internal Data Migrations of Flash Devices via Lifetime-Retention Harmonization
IEEE transactions on computers, 2021-03, Vol.70 (3), p.428-439
2021
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Planting Fast-Growing Forest by Leveraging the Asymmetric Read/Write Latency of NVRAM-Based Systems
IEEE transactions on computer-aided design of integrated circuits and systems, 2022-10, Vol.41 (10), p.3304-3317
2022
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Scrubbing-Aware Secure Deletion for 3-D NAND Flash
IEEE transactions on computer-aided design of integrated circuits and systems, 2018-11, Vol.37 (11), p.2790-2801
2018
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wrJFS: A Write-Reduction Journaling File System for Byte-addressable NVRAM
IEEE transactions on computers, 2018-07, Vol.67 (7), p.1023-1038
2018
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Beyond Write-Reduction Consideration: A Wear-Leveling-Enabled B⁺-Tree Indexing Scheme Over an NVRAM-Based Architecture
IEEE transactions on computer-aided design of integrated circuits and systems, 2021-12, Vol.40 (12), p.2455-2466
2021
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On Minimizing Analog Variation Errors to Resolve the Scalability Issue of ReRAM-Based Crossbar Accelerators
IEEE transactions on computer-aided design of integrated circuits and systems, 2020-11, Vol.39 (11), p.3856-3867
2020
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mwJFS: A Multiwrite-Mode Journaling File System for MLC NVRAM Storages
IEEE transactions on very large scale integration (VLSI) systems, 2019-09, Vol.27 (9), p.2060-2073
2019
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B-Sort: Enabling Write-Once Sorting for Nonvolatile Memory
IEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.4549-4562
2020
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Boosting NVDIMM Performance With a Lightweight Caching Algorithm
IEEE transactions on very large scale integration (VLSI) systems, 2018-08, Vol.26 (8), p.1518-1530
2018
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An Erase Efficiency Boosting Strategy for 3D Charge Trap NAND Flash
IEEE transactions on computers, 2018-09, Vol.67 (9), p.1246-1258
2018
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Enabling Write-Reduction Multiversion Scheme With Efficient Dual-Range Query Over NVRAM
IEEE transactions on very large scale integration (VLSI) systems, 2021-06, Vol.29 (6), p.1244-1256
2021
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Antiwear Leveling Design for SSDs With Hybrid ECC Capability
IEEE transactions on very large scale integration (VLSI) systems, 2017-02, Vol.25 (2), p.488-501
2017
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Co-Optimizing Storage Space Utilization and Performance for Key-Value Solid State Drives
IEEE transactions on computer-aided design of integrated circuits and systems, 2019-01, Vol.38 (1), p.29-42
2019
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A Partial Page Cache Strategy for NVRAM-Based Storage Devices
IEEE transactions on computer-aided design of integrated circuits and systems, 2020-02, Vol.39 (2), p.373-386
2020
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Efficient Warranty-Aware Wear Leveling for Embedded Systems With PCM Main Memory
IEEE transactions on very large scale integration (VLSI) systems, 2016-07, Vol.24 (7), p.2535-2547
2016
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