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Approximation Algorithm for Scheduling a Chain of Tasks on Heterogeneous Systems

Euro-Par 2017: Parallel Processing Workshops, 2018, p.353-365

2018

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Polynomial Scheduling Algorithm for Parallel Applications on Hybrid Platforms

Combinatorial Optimization, p.143-155

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Co-simulation of a Model Predictive Control System for Automotive Applications

Software Engineering and Formal Methods. SEFM 2021 Collocated Workshops, 2022, p.204-220

2022

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Case Studies on the Impact and Challenges of Heterogeneous NUMA Architectures for HPC

Architecture of Computing Systems, p.251-265

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Task management on fully heterogeneous micro‐server system: Modeling and resolution strategies

Concurrency and computation, 2018-12, Vol.30 (23), p.n/a

2018

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Hypergraph Clustering with Path-Length Awareness

Computational Science – ICCS 2024, p.90-104

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Cross-level Co-simulation and Verification of an Automatic Transmission Control on Embedded Processor

Software Engineering and Formal Methods. SEFM 2020 Collocated Workshops, p.263-279

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Design Space Exploration of HPC Systems with Random Forest-based Bayesian Optimization

Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024, p.9-15

2024

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A C Subset for Ergonomic Source-to-Source Analyses and Transformations

Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024, p.1-8

2024

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NQC²: A Non-Intrusive QEMU Code Coverage Plugin

Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024, p.16-21

2024

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Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs

Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024, p.29-34

2024

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Using Source-to-Source to Target RISC-V Custom Extensions: UVE Case-Study

Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024, p.42-50

2024

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Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation

Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024, p.35-41

2024

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Integration of RISC-V Page Table Walk in gem5 SE Mode

Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024, p.22-28

2024

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An Innovative Methodology for Scan Chain Insertion and Analysis at RTL

2011 Asian Test Symposium, 2011, p.66-71

2011

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Decoupling processor and memory hierarchy simulators for efficient design space exploration

System Engineering for constrained embedded systems, 2022, p.47-52

2022

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A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors

2023 26th Euromicro Conference on Digital System Design (DSD), 2023, p.756-763

2023

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Multi-start simulated annealing for partially-reconfigurable FPGA floorplanning

2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2018, p.1335-1338

2018

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Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design

2024

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A Hypergraph Model and Associated Optimization Strategies for Path Length-Driven Netlist Partitioning

Computational Science – ICCS 2023, p.652-660

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Approximation Algorithm for Scheduling Applications on Hybrid Multi-core Machines with Communications Delays

2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2018, p.36-45

2018

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Multilevel simulation-based co-design of next generation HPC microprocessors

2021 International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS), 2021, p.18-29

2021

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3DIP: An iterative partitioning tool for monolithic 3D IC

2016 IEEE International 3D Systems Integration Conference (3DIC), 2016, p.1-5

2016

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Modeling of Applications and Hardware to Explore Task Mapping and Scheduling Strategies on a Heterogeneous Micro-Server System

2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2017, p.65-76

2017

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A complete methodology for determining memory BIST optimization under wrappers sharing constraints

2011 3rd Asia Symposium on Quality Electronic Design (ASQED), 2011, p.46-53

2011

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Approximation Algorithm for Scheduling a Chain of Tasks on Heterogeneous Systems

Polynomial Scheduling Algorithm for Parallel Applications on Hybrid Platforms

Co-simulation of a Model Predictive Control System for Automotive Applications

Case Studies on the Impact and Challenges of Heterogeneous NUMA Architectures for HPC

Task management on fully heterogeneous micro‐server system: Modeling and resolution strategies

Hypergraph Clustering with Path-Length Awareness

Cross-level Co-simulation and Verification of an Automatic Transmission Control on Embedded Processor

Design Space Exploration of HPC Systems with Random Forest-based Bayesian Optimization

A C Subset for Ergonomic Source-to-Source Analyses and Transformations

NQC²: A Non-Intrusive QEMU Code Coverage Plugin

Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs

Using Source-to-Source to Target RISC-V Custom Extensions: UVE Case-Study

Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation

Integration of RISC-V Page Table Walk in gem5 SE Mode

An Innovative Methodology for Scan Chain Insertion and Analysis at RTL

Decoupling processor and memory hierarchy simulators for efficient design space exploration

A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors

Multi-start simulated annealing for partially-reconfigurable FPGA floorplanning

Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design

A Hypergraph Model and Associated Optimization Strategies for Path Length-Driven Netlist Partitioning

Approximation Algorithm for Scheduling Applications on Hybrid Multi-core Machines with Communications Delays

Multilevel simulation-based co-design of next generation HPC microprocessors

3DIP: An iterative partitioning tool for monolithic 3D IC

Modeling of Applications and Hardware to Explore Task Mapping and Scheduling Strategies on a Heterogeneous Micro-Server System

A complete methodology for determining memory BIST optimization under wrappers sharing constraints

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