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Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells

IEEE access, 2019, Vol.7, p.17312-17327

2019

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Novel direct designs for 3-input XOR function for low-power and high-speed applications

International journal of electronics, 2010-06, Vol.97 (6), p.647-662

2010

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Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

VLSI Design, 2010-01, Vol.2010 (2010), p.1-17

2010

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Cell design methodology (CDM) for balanced Carry-InverseCarry circuits in hybrid-CMOS logic style

International journal of electronics, 2014-10, Vol.101 (10), p.1357-1374

2014

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Area-power and Energy Efficient Substitution box (S-box) in Advanced Encryption Standard (AES)

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.263-267

2024

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Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR Circuits in Hybrid-CMOS Logic Style

Journal of low-power electronics, 2010-12, Vol.6 (4), p.503-512

2010

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Wireless radar devices for smart human-computer interaction

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014, p.65-68

2014

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Processing-in-Memory Designs Based on Emerging Technology for Efficient Machine Learning Acceleration

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.614-619

2024

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Flip-Lock: A Flip-Flop-Based Logic Locking Technique for Thwarting ML-based and Algorithmic Structural Attacks

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.185-191

2024

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Enhancing Long Sequence Input Processing in FPGA-Based Transformer Accelerators through Attention Fusion

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.599-603

2024

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IRET: Incremental Resolution Enhancing Transformer

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.620-625

2024

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EPIC: Efficient and Proactive Instruction-level Cyberdefense

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.409-414

2024

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Dynamic Multi-FPGA Prototyping Platforms with Simultaneous Networking, Placement and Routing

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.433-439

2024

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Modular Security Evaluation Platform for Physiological Closed-Loop Control Systems

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.682-687

2024

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ControLayout: Conditional Diffusion for Style-Controllable and Violation-Fixable Layout Pattern Generation

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.511-515

2024

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Feature Fusion based Hotspot Detection with R-EfficientNet

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.446-451

2024

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A Cryptographic Hardware Engineering Course based on FPGA and Security Analysis Equipment

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.706-711

2024

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EDA-schema: A Graph Datamodel Schema and Open Dataset for Digital Design Automation

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.69-77

2024

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Transductive Spiking Graph Neural Networks for Loihi

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.608-613

2024

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A DRAM-based Near-Memory Architecture for Accelerated and Energy-Efficient Execution of Transformers

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.57-62

2024

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Assert-O: Context-based Assertion Optimization using LLMs

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.233-239

2024

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MARS: MAximizing throughput for MPPT-based self-sustaining LoRa Systems

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.105-110

2024

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SCRIPT: A Multi-Objective Routing Framework for Securing Chiplet Systems against Distributed DoS Attacks

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.78-85

2024

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Hybrid Magneto-electric FET-CMOS Integrated Memory Design for Instant-on Computing

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.770-775

2024

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SSFuzz:Generating syntactic and semantic seeds for RISC-V processors

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, p.421-426

2024

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Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells

Novel direct designs for 3-input XOR function for low-power and high-speed applications

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Cell design methodology (CDM) for balanced Carry-InverseCarry circuits in hybrid-CMOS logic style

Area-power and Energy Efficient Substitution box (S-box) in Advanced Encryption Standard (AES)

Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR Circuits in Hybrid-CMOS Logic Style

Wireless radar devices for smart human-computer interaction

Processing-in-Memory Designs Based on Emerging Technology for Efficient Machine Learning Acceleration

Flip-Lock: A Flip-Flop-Based Logic Locking Technique for Thwarting ML-based and Algorithmic Structural Attacks

Enhancing Long Sequence Input Processing in FPGA-Based Transformer Accelerators through Attention Fusion

IRET: Incremental Resolution Enhancing Transformer

EPIC: Efficient and Proactive Instruction-level Cyberdefense

Dynamic Multi-FPGA Prototyping Platforms with Simultaneous Networking, Placement and Routing

Modular Security Evaluation Platform for Physiological Closed-Loop Control Systems

ControLayout: Conditional Diffusion for Style-Controllable and Violation-Fixable Layout Pattern Generation

Feature Fusion based Hotspot Detection with R-EfficientNet

A Cryptographic Hardware Engineering Course based on FPGA and Security Analysis Equipment

EDA-schema: A Graph Datamodel Schema and Open Dataset for Digital Design Automation

Transductive Spiking Graph Neural Networks for Loihi

A DRAM-based Near-Memory Architecture for Accelerated and Energy-Efficient Execution of Transformers

Assert-O: Context-based Assertion Optimization using LLMs

MARS: MAximizing throughput for MPPT-based self-sustaining LoRa Systems

SCRIPT: A Multi-Objective Routing Framework for Securing Chiplet Systems against Distributed DoS Attacks

Hybrid Magneto-electric FET-CMOS Integrated Memory Design for Instant-on Computing

SSFuzz:Generating syntactic and semantic seeds for RISC-V processors

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