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A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016, p.1-2

2016

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A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW

2018 IEEE Symposium on VLSI Circuits, 2018, p.183-184

2018

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A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS

2019 IEEE Custom Integrated Circuits Conference (CICC), 2019, p.1-4

2019

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IEEE_Xplore

A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.448-450

2018

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IEEE_Xplore

A 0.5ps 1.4mW 50MS/s Nyquist bandwidth time amplifier based two-step flash-ΔΣ time-to-digital converter

2016 Second International Conference on Event-based Control, Communication, and Signal Processing (EBCCSP), 2016, p.1-4

2016

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IEEE_Xplore

A 0.5V 0.5mW switching current source oscillator

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, p.183-186

2015

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A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS

2017 Symposium on VLSI Circuits, 2017, p.C178-C179

2017

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A 1/f Noise Upconversion Reduction Technique

RF CMOS Oscillators for Modern Wireless Applications, 2019, p.87-121

1, 2019

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A 1 V Bandgap Reference in 7-nm FinFET with a Programmable Temperature Coefficient and an Inaccuracy of ±0.2% from −45°C to 125°C

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), 2018, p.78-81

2018

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IEEE_Xplore

A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-ΔΣ time-to-digital converter for ADPLL

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, p.95-98

2015

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A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS

2014 Symposium on VLSI Circuits Digest of Technical Papers, 2014, p.1-2

2014

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IEEE_Xplore

14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3

2015

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IEEE_Xplore

15.5 Cryo-CMOS circuits and systems for scalable quantum computing

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.264-265

2017

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IEEE_Xplore

A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2017, p.93-96

2017

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17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and −250dB FoM

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.276-278

2020

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IEEE_Xplore

An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

2023

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IEEE_Xplore

A 184.6-dBc/Hz FoM 100-kHz Flicker Phase Noise Corner 30-GHz Rotary Traveling-Wave Oscillator Using Distributed Stubs in 22-nm FD-SOI

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019, p.103-106

2019

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IEEE_Xplore

19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.332-333

2017

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IEEE_Xplore

A 2×13-bit all-digital I/Q RF-DAC in 65-nm CMOS

2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2013, p.167-170

2013

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IEEE_Xplore

A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA

2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2018, p.293-294

2018

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A 2.4GHz class-D power amplifier with conduction angle calibration for −50dBc harmonic emissions

2014 IEEE Radio Frequency Integrated Circuits Symposium, 2014, p.239-242

2014

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IEEE_Xplore

A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.380-382

2022

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IEEE_Xplore

24.1 A 770pJ/b 0.85V 0.3mm2 DCO-based phase-tracking RX featuring direct demodulation and data-aided carrier tracking for IoT applications

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.408-409

2017

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IEEE_Xplore

A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter−N of -269.3 dB

2021 Symposium on VLSI Circuits, 2021, p.1-2

2021

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IEEE_Xplore

25.4 A 1/f noise upconversion reduction technique applied to Class-D and Class-F oscillators

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3

2015

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IEEE_Xplore

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A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS

A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW

A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS

A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference

A 0.5ps 1.4mW 50MS/s Nyquist bandwidth time amplifier based two-step flash-ΔΣ time-to-digital converter

A 0.5V 0.5mW switching current source oscillator

A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS

A 1/f Noise Upconversion Reduction Technique

A 1 V Bandgap Reference in 7-nm FinFET with a Programmable Temperature Coefficient and an Inaccuracy of ±0.2% from −45°C to 125°C

A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-ΔΣ time-to-digital converter for ADPLL

A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS

14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S

15.5 Cryo-CMOS circuits and systems for scalable quantum computing

A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS

17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and −250dB FoM

An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM

A 184.6-dBc/Hz FoM 100-kHz Flicker Phase Noise Corner 30-GHz Rotary Traveling-Wave Oscillator Using Distributed Stubs in 22-nm FD-SOI

19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications

A 2×13-bit all-digital I/Q RF-DAC in 65-nm CMOS

A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA

A 2.4GHz class-D power amplifier with conduction angle calibration for −50dBc harmonic emissions

A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs

24.1 A 770pJ/b 0.85V 0.3mm2 DCO-based phase-tracking RX featuring direct demodulation and data-aided carrier tracking for IoT applications

A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter−N of -269.3 dB

25.4 A 1/f noise upconversion reduction technique applied to Class-D and Class-F oscillators

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