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Layout impact on the performance of a locally strained PMOSFET

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005, 2005, p.22-23

2005

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O2 post deposition anneal of Al2O3 blocking dielectric for higher performance and reliability of TANOS Flash memory

2009 Proceedings of the European Solid State Device Research Conference, 2009, p.272-275

2009

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Scaling Down of MOCVD HfSiON to 1nm EOT

ECS transactions, 2007, Vol.11 (4), p.13-24

2007

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Laser-annealed junctions with advanced CMOS gate stacks for 32nm Node: Perspectives on device performance and manufacturability

2008 Symposium on VLSI Technology, 2008, p.186-187

2008

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Study of Ni-Silicide Contacts to Si:C Source/Drain

ECS transactions, 2006, Vol.3 (2), p.139-147

2006

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Analysis of As, P Diffusion and Defect Evolution during Sub-millisecond Non-melt Laser Annealing based on an Atomistic Kinetic Monte Carlo Approach

2007 IEEE International Electron Devices Meeting, 2007, p.955-958

2007

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Diode Analysis of Electrically Active Defects in Recessed SiGe Source/Drain Diodes

ECS transactions, 2006, Vol.3 (7), p.655-665

2006

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Ultra-Shallow Junctions Formed by Co-Implantation and Sub-Melt Laser Annealing

ECS transactions, 2006, Vol.3 (2), p.105-112

2006

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A systematic study of trade-offs in engineering a locally strained pMOSFET

IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004, 2004, p.1055-1058

2004

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Pre-amorphization damage in ion-implanted silicon

Materials science reports, 1991-08, Vol.6 (7), p.275-366

1991

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Study of pulsed RF DPN process parameters for 65 nm node MOSFET gate dielectrics

MRS proceedings, 2004, Vol.811, Article D2.10

2004

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Improvement of the CMOS characteristics of bulk Si FinFETs by high temperature ion implantation

2016 IEEE International Electron Devices Meeting (IEDM), 2016, p.17.5.1-17.5.4

2016

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Silicide yield improvement with NiPtSi formation by laser anneal for advanced low power platform CMOS technology

2009 IEEE International Electron Devices Meeting (IEDM), 2009, p.1-4

2009

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Analysis of Dopant Diffusion and Defect Evolution during sub-millisecond Non-melt Laser Annealing based on an Atomistic Kinetic Monte Carlo Approach

2006 International Electron Devices Meeting, 2006, p.1-4

2006

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Laser Annealed Junctions: Process Integration Sequence Optimization for Advanced CMOS Technologies

2007 International Workshop on Junction Technology, 2007, p.137-140

2007

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Advanced 2D/3D simulations for laser annealed device using an atomistic kinetic Monte Carlo approach and Scanning Spreading Resistance Microscopy (SSRM)

2008 IEEE International Electron Devices Meeting, 2008, p.1-4

2008

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Optimization of Sub-Melt Laser Anneal: Performance and Reliability

2006 International Electron Devices Meeting, 2006, p.1-4

2006

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Thermal Stability of CoSi2 on Submicron Polycrystalline Silicon Lines

ESSDERC '92: 22nd European Solid State Device Research conference, 1992, p.665-668

1992

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Junction anneal sequence optimization for advanced high-k / metal gate CMOS technology

2009 International Workshop on Junction Technology, 2009, p.54-57

2009

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Investigation of an in-situ probe for phase transformations during RTP silicidation

MRS proceedings, 1992, Vol.260, Article 145

1992

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In-situ emissivity and temperature measurement during rapid thermal processing (RTP)

MRS proceedings, 1992, Vol.260, Article 653

1992

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Avoiding Dislocation Formation for B, P, and As Implants in Silicon

MRS proceedings, 1991, Vol.235, Article 173

1991

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Impact of sub-melt laser annealing on Si1-xGex source /drain defectivity

2007 15th International Conference on Advanced Thermal Processing of Semiconductors, 2007, p.307-315

2007

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Impact of Cu contacts on front-end performance: a projection towards 22nm node

2006 International Interconnect Technology Conference, 2006, p.178-180

2006

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Impact of Etching Depth on the Leakage Current of Recessed SiGe Junctions

2006 International SiGe Technology and Device Meeting, 2006, p.1-2

2006

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Layout impact on the performance of a locally strained PMOSFET

O2 post deposition anneal of Al2O3 blocking dielectric for higher performance and reliability of TANOS Flash memory

Scaling Down of MOCVD HfSiON to 1nm EOT

Laser-annealed junctions with advanced CMOS gate stacks for 32nm Node: Perspectives on device performance and manufacturability

Study of Ni-Silicide Contacts to Si:C Source/Drain

Analysis of As, P Diffusion and Defect Evolution during Sub-millisecond Non-melt Laser Annealing based on an Atomistic Kinetic Monte Carlo Approach

Diode Analysis of Electrically Active Defects in Recessed SiGe Source/Drain Diodes

Ultra-Shallow Junctions Formed by Co-Implantation and Sub-Melt Laser Annealing

A systematic study of trade-offs in engineering a locally strained pMOSFET

Pre-amorphization damage in ion-implanted silicon

Study of pulsed RF DPN process parameters for 65 nm node MOSFET gate dielectrics

Improvement of the CMOS characteristics of bulk Si FinFETs by high temperature ion implantation

Silicide yield improvement with NiPtSi formation by laser anneal for advanced low power platform CMOS technology

Analysis of Dopant Diffusion and Defect Evolution during sub-millisecond Non-melt Laser Annealing based on an Atomistic Kinetic Monte Carlo Approach

Laser Annealed Junctions: Process Integration Sequence Optimization for Advanced CMOS Technologies

Advanced 2D/3D simulations for laser annealed device using an atomistic kinetic Monte Carlo approach and Scanning Spreading Resistance Microscopy (SSRM)

Optimization of Sub-Melt Laser Anneal: Performance and Reliability

Thermal Stability of CoSi2 on Submicron Polycrystalline Silicon Lines

Junction anneal sequence optimization for advanced high-k / metal gate CMOS technology

Investigation of an in-situ probe for phase transformations during RTP silicidation

In-situ emissivity and temperature measurement during rapid thermal processing (RTP)

Avoiding Dislocation Formation for B, P, and As Implants in Silicon

Impact of sub-melt laser annealing on Si1-xGex source /drain defectivity

Impact of Cu contacts on front-end performance: a projection towards 22nm node

Impact of Etching Depth on the Leakage Current of Recessed SiGe Junctions

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