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Dipole Moment Model Explaining nFET Vt Tuning Utilizing La, Sc, Er, and Sr Doped HfSiON Dielectrics

2007 IEEE Symposium on VLSI Technology, 2007, p.68-69

2007

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Strain additivity in III-V channels for CMOSFETs beyond 22nm technology node

2008 Symposium on VLSI Technology, 2008, p.182-183

2008

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Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme

2007 IEEE Symposium on VLSI Technology, 2007, p.154-155

2007

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Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT

2008 Symposium on VLSI Technology, 2008, p.82-83

2008

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Systematic investigation of amorphous transition-metal-silicon-nitride electrodes for metal gate CMOS applications

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005, 2005, p.46-47

2005

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New hot-carrier degradation phenomenon in nano-scale floating body MOSFETS

2008 IEEE International Reliability Physics Symposium, 2008, p.739-740

2008

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Detection of Electron Trap Generation due to Constant Voltage Stress on High-κ Gate Stacks

2006 IEEE International Reliability Physics Symposium Proceedings, 2006, p.169-173

2006

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Impact of Bottom Interfacial Layer on the Threshold Voltage and Device Reliability of Fluorine Incorporated PMOSFETS with High-K/Metal Gate

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, 2007, p.374-377

2007

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The effects of Ge composition and Si cap thickness on hot carrier reliability of Si/Si1-xGex/Si p-MOSFETs with high-K/metal gate

2008 Symposium on VLSI Technology, 2008, p.56-57

2008

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Comparison of NMOS and PMOS stress for determining the source of NBTI in TiN/HfSiON devices [MOSFETs]

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual, 2005, p.80-83

2005

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Systematic Gate Stack Optimization to Maximize Mobility with HfSiON EOT Scaling

2006 European Solid-State Device Research Conference, 2006, p.113-116

2006

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Realiability Characteristics of Metal/High-K Pmos with Top Interface Engineered Band Offset Dielectric (BOD)

2006 IEEE International Reliability Physics Symposium Proceedings, 2006, p.661-662

2006

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Detection of trap generation in high-k gate stacks

2005 IEEE International Integrated Reliability Workshop, 2005, p.5 pp.

2005

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Comparison of hot carrier stress and constant voltage stress in Hf-silicate NMOS transistors with poly and TiN gate stack

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual, 2005, p.638-639

2005

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Demonstration of high performance transistors with PVD metal gate

Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005, 2005, p.431-434

2005

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Recovery of NBTI degradation in HfSiON/metal gate transistors

IEEE International Integrated Reliability Workshop Final Report, 2004, 2004, p.132-135

2004

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Conditions of employment in English banking, recruitment, training promotion, staff management relations

Harris, H.R

1960

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High Performance pMOSFETs Using Si/Si1-xGex/Si Quantum Wells with High-k/Metal Gate Stacks and Additive Uniaxial Strain for 22 nm Technology Node

2007 IEEE International Electron Devices Meeting, 2007, p.727-730

2007

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Enhanced Performance and SRAM Stability in FinFET with Reduced Process Steps for Source/Drain Doping

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2008, p.20-21

2008

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Device and reliability improvement of HfSiON+LaOx/metal gate stacks for 22nm node application

2008 IEEE International Electron Devices Meeting, 2008, p.1-4

2008

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High mobility SiGe shell-Si core omega gate pFETS

2009 International Symposium on VLSI Technology, Systems, and Applications, 2009, p.136-138

2009

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Flexible, simplified CMOS on Si(110) with metal gate / high k for HP and LSTP

2007 IEEE International Electron Devices Meeting, 2007, p.57-60

2007

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Understanding Strain Effects on Double-Gate FinFET Drive-Current Enhancement, Hot-Carrier Reliability and Ring-Oscillator Delay Performance via Uniaxial Wafer Bending Experiments

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2008, p.163-164

2008

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Gate First Band Edge High-k/Metal Stacks with EOT=0.74nm for 22nm Node nFETs

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2008, p.152-153

2008

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Simplified manufacturable band edge metal gate solution for NMOS without a capping layer

2006 International Electron Devices Meeting, 2006, p.1-4

2006

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Dipole Moment Model Explaining nFET Vt Tuning Utilizing La, Sc, Er, and Sr Doped HfSiON Dielectrics

Strain additivity in III-V channels for CMOSFETs beyond 22nm technology node

Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme

Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT

Systematic investigation of amorphous transition-metal-silicon-nitride electrodes for metal gate CMOS applications

New hot-carrier degradation phenomenon in nano-scale floating body MOSFETS

Detection of Electron Trap Generation due to Constant Voltage Stress on High-κ Gate Stacks

Impact of Bottom Interfacial Layer on the Threshold Voltage and Device Reliability of Fluorine Incorporated PMOSFETS with High-K/Metal Gate

The effects of Ge composition and Si cap thickness on hot carrier reliability of Si/Si1-xGex/Si p-MOSFETs with high-K/metal gate

Comparison of NMOS and PMOS stress for determining the source of NBTI in TiN/HfSiON devices [MOSFETs]

Systematic Gate Stack Optimization to Maximize Mobility with HfSiON EOT Scaling

Realiability Characteristics of Metal/High-K Pmos with Top Interface Engineered Band Offset Dielectric (BOD)

Detection of trap generation in high-k gate stacks

Comparison of hot carrier stress and constant voltage stress in Hf-silicate NMOS transistors with poly and TiN gate stack

Demonstration of high performance transistors with PVD metal gate

Recovery of NBTI degradation in HfSiON/metal gate transistors

Conditions of employment in English banking, recruitment, training promotion, staff management relations

High Performance pMOSFETs Using Si/Si1-xGex/Si Quantum Wells with High-k/Metal Gate Stacks and Additive Uniaxial Strain for 22 nm Technology Node

Enhanced Performance and SRAM Stability in FinFET with Reduced Process Steps for Source/Drain Doping

Device and reliability improvement of HfSiON+LaOx/metal gate stacks for 22nm node application

High mobility SiGe shell-Si core omega gate pFETS

Flexible, simplified CMOS on Si(110) with metal gate / high k for HP and LSTP

Understanding Strain Effects on Double-Gate FinFET Drive-Current Enhancement, Hot-Carrier Reliability and Ring-Oscillator Delay Performance via Uniaxial Wafer Bending Experiments

Gate First Band Edge High-k/Metal Stacks with EOT=0.74nm for 22nm Node nFETs

Simplified manufacturable band edge metal gate solution for NMOS without a capping layer

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